AK8186B Datasheet, PDF (64/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
VCO Divider and CLK Input
Register
Address Bit(s)
(Hex)
Name
0x1E0 2:0 ^{VCO Divider}
0x1E1
Power-Down
4 Clock Input
Section
Power-Down
3 VCO clock
interface
Power-Down
2 _{VCO and CLK}
Select
1 _{VCO or CLK}
Bypass
0 _{VCO divider}
Description
[2:1:0]
000
001
010
011
100
101
110
111
Divide
2
3
4 (default)
5
6
Output Static
Output Static
Output Static
Powers down the clock input section (including CLK buffer, VCO dividers and
CLK tree).
0 : normal operation (default).
1 : Power-down.
Powers down the interface block between VCO and clock distribution.
0 : normal operation (default).
1 : power-down.
Powers down both VCO and CLK input.
0 : normal operation (default).
1 : power-down.
Powers down the clock input section (including CLK buffer, VCO dividers and
CLK tree).
0 : Selects external CLK as input to VCO divider (default).
1 : Selects VCO as input to VCO divider; cannot bypass VCO divider when
this is selected.
Bypasses or uses the VCO divider.
0 : Uses VCO divider (default).
1 : Bypasses VCO divider; cannnot select VCO as input when this is selected.
Sep-2012
- 64 -
draft-E-02