AK8186B Datasheet, PDF (26/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
LOCK DETECT
The AK8186B has three kinds of lock detect function. Each Lock Detect function is able to report to LD,
STATUS and REFMON pins.
.Table 20 Registers for Lock Detect
Mode
Digital Lock Detect (DLD)
Current Source DLD (CLD)
Analog Lock Detect (ALD)
Enable/Disable
Register
0x18[3]
---
---
LD
0x1A[5:0]



OUTPUT pin
STATUS
0x17[7:2]

REFMON
0x1B<4:0>

Digital Lock Detect (DLD)
The Digital Lock Detect function detects a lock when the phase difference of the rising edges at the PFD
inputs is less than the Lock Detect Window (3.5ns typical). The lock is indicated when the number of
consecutive “lock detection” reaches the threshold of the Lock Detect Counter defined by 0x18<6:5>.
The “unlock” is indicated when the DLD function detects the larger phase difference at the PFD inputs than
the Lock Detect Window. The unlock threshold is just one value.
Figure 15. Digital Lock Detect
Current Source Digital Lock Detect (CLD)
The lock indication by the DLD is normally not stable until the PLL gets in lock completely. In some
application, it might be required to get a lock detect after the PLL gets solidly locked. The Current Source
DLD function (CLD) could be useful for that requirement.
The CLD provides a current of 110uA to LD pin when the DLD detects a lock (DLD = H). While the PLL
continues to be in lock state, the voltage of LD is going up with the current. But if the PLL is back to unlock
state, the charge on a capacitor externally connected to LD is discharged instantly.
The voltage of LD can be sensed by an internal or external comparator. When the internal LD pin
comparator is used (0x1D[3]=1b), its output can be read at STATUS pin (0x17[7:2]) or REFMON pin
Sep-2012
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