AK8186B Datasheet, PDF (43/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

REGISTER MAP
Addr
(HEX)
Parameter
Serial Control Port
Bit 7
00
Serial Port
Configuration
SDO Active
01
02
03
04
Read Back
Control
PLL
10 PFD & CP
PFD Polarity
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LSB
Soft
Long
Long
Soft
First
Reset
Instruction
Instruction
Reset
Blank
Reserved
Part ID (read only)
Blank
Charge Pump Current
Charge Pump Mode
AK8186B
Bit 1
LSB
First
Bit 0
Default
Value
SDO
Active
18
43
Read Back
Active
00
Registers
PLL Power Down
7D
11 R Counter
14-bit R Divider Bits<7:0>
01
12
Blank
14-bit R Divider Bits<13:8>
00
13 A Counter
Blank
6-bit A counter
00
14 B Counter
13-bit B counter Bits<7:0>
03
15
Blank
13-bit B counter Bits<12:8>
00
16
PLL Control 1
Set CP Pin
To VDD/2
Reset R
Counter
Reset A&B
Counters
Reset All
Counters
B Counter
Bypass
Prescaler P
06
17 PLL Control 2
STATUS Pin Control
Reserved
00
18 PLL Control 3 Reserved
Lock Detect Counter
Digital Lock
Detect
Window
Disable
Digital Lock
Detect
VCO Calibration Divider
19 PLL Control 4
R,A,B Counters _SYNC
Pin Reset
1A PLL Control 5 Reserved
VCO
1B PLL Control 6 Frequency
Monitor
Reference
Frequency
Monitor
Threshold
REF2
Frequency
Monitor
1C PLL Control 7
Blank
Select
REF2
1D PLL Control 8
Reserved
REF1
Frequency
Monitor
Use
REF_SEL
Pin
Reserved
Reserved
LD Pin Control
REFMON Pin Control
Automatic
Reference
Switchover
PLL Status
Register
Disable
Stay on
REF2
LD Pin
Comparator
Enable
REF2
Power On
Holdover
Enable
REF1
Power On
External
Holdover
Control
VCO Cal
Now
06
00
00
00
Differential
Reference
00
Holdover
Enable
00
1E PLL Control 9
Reserved
00
1F
PLL
Readback
20 to
4F
Reserved
VCO Cal
Finished
Holdover
Active
REF2
Selected
VCO
Frequency
Threshold
Blank
REF2
Frequency
Threshold
REF1
Frequency
Threshold
Digital
Lock
--
Detect
draft-E-02
- 43 -
Sep-2012