HMC7044 Datasheet, PDF (9/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Parameter
Min
OPEN-LOOP VCO PHASE NOISE
fOUT = 2457.6 MHz
fOFFSET = 100 kHz
fOFFSET = 800 kHz
fOFFSET = 1 MHz
fOFFSET = 10 MHz
Normalized Phase Noise Variation vs.
Frequency
Phase Noise Variation vs. Temperature
Phase Noise Degradation in Low
Performance Mode
Typ
Max
−109
−134
−136
−156
±2
±2
2
Unit Test Conditions/Comments
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dB
dB
dB
High performance mode, does not include
floor contribution due to output network
Sweep across both VCOs, all bands;
normalize to 2457.6 MHz
1 _{Guaranteed by design and characterization.}
2 _{Although the device covers this range without any gaps, for frequencies between ~2700 Hz and 2900 Hz, using a different VCO core to synthesize the frequency can}
be required as process parameters shift. Features are built into the HMC7044 to determine which core is selected for a given frequency that can fall in this range, but it
can require software to configure these circuits appropriately.
CLOCK OUTPUT DISTRIBUTION CHARACTERISTICS
Table 7.
Parameter
Min Typ
CLOCK OUTPUT SKEW
CLKOUTx/CLKOUTx to SCLKOUTx/SCLKOUTx
15
Skew within One Clock Output Pair
Any CLKOUTx/CLKOUTx to Any
30
SCLKOUTx/SCLKOUTx
CLOCK OUTPUT DIVIDER
12-Bit Divider Range
1
SYSREF CLOCK OUTPUT DIVIDER
12-Bit Divider Range
1
Max Unit
|ps|
|ps|
4094
4094
CLOCK OUTPUT ANALOG FINE DELAY
Analog Fine Delay
Adjustment Range¹
135
670
Resolution
25
Maximum Analog Fine Delay Frequency¹
3200
CLOCK OUTPUT COARSE DELAY (FLIP FLOP
BASED)
Coarse Delay Adjustment Range
0
17
Coarse Delay Resolution
Maximum Frequency Coarse Delay¹
CLOCK OUTPUT COARSE DELAY (SLIP BASED)
Coarse Delay
Adjustment Range
Resolution
Maximum Frequency Coarse Delay
1 _{Guaranteed by design and characterization.}
169.54
3200
1 to ∞
339.08
1600
ps
ps
MHz
½ VCO
period
ps
MHz
VCO period
ps
MHz
Test Conditions/Comments
Same pair, same type termination and
configuration
Any pair, same type termination and configuration
1, 3, 5, and all even numbers up to 4094
1, 3, 5 and all even numbers up to 4094; pulse
generator behavior is only supported for divide
ratios ≥ 32
24 delay steps, fCLKOUT = 983.04 MHz
fCLKOUT = 983.04 MHz (2949.12 MHz/3)
17 delay steps in ½ VCO period
fVCO = 2949.12 MHz
fVCO = 2949.12 MHz
Rev. B | Page 9 of 72