HMC7044 Datasheet, PDF (15/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Pin No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Mnemonic
SCLK
SDATA
VCC3_SYSREF
SCLKOUT5
SCLKOUT5
CLKOUT4
CLKOUT4
VCC4_OUT
CLKOUT6
CLKOUT6
SCLKOUT7
SCLKOUT7
GPIO1
CPOUT1
CLKIN3
CLKIN3
RSV
CLKIN1/FIN
CLKIN1/FIN
VCC5_PLL1
CLKIN0/RFSYNCIN
CLKIN0/RFSYNCIN
VCC6_OSCOUT
CLKIN2/OSCOUT0
CLKIN2/OSCOUT0
OSCOUT1
OSCOUT1
LDOBYP6
OSCIN
OSCIN
LDOBYP7
CPOUT2
VCC7_PLL2
GPIO2
SCLKOUT9
SCLKOUT9
CLKOUT8
CLKOUT8
VCC8_OUT
CLKOUT10
CLKOUT10
SCLKOUT11
SCLKOUT11
GPIO3
GPIO4
SCLKOUT13
Type¹
I
I/O
P
O
O
O
O
P
O
O
O
O
I/O
O
I
I
R
I
I
P
I
I
P
I/O
I/O
O
O
I
I
I/O
P
I/O
O
O
O
O
P
O
O
O
O
I/O
I/O
O
Description
SPI Clock.
SPI Data.
Power Supply for Common SYSREF Divider.
True Clock Output Channel 5. Default SYSREF profile.
Complementary Clock Output Channel 5. Default SYSREF profile.
True Clock Output Channel 4. Default DCLK profile.
Complementary Clock Output Channel 4. Default DCLK profile.
Power Supply for Clock Group 2 (South)—Channel 4, Channel 5, Channel 6, and Channel 7. See the
Clock Grouping, Skew, and Crosstalk section.
True Clock Output Channel 6. Default DCLK profile.
Complementary Clock Output Channel 6. Default DCLK profile.
True Clock Output Channel 7. Default SYSREF profile.
Complementary Clock Output Channel 7. Default SYSREF profile.
Programmable General-Purpose Input/Output 1.
PLL1 Charge Pump Output.
True Reference Clock Input 3 of PLL1.
Complementary Reference Clock Input 3 of PLL1.
Reserved Pin. This pin must be tied to ground.
True Reference Clock Input 1 of PLL1/External VCO Input for External VCO Mode.
Complementary Reference Clock Input 1 of PLL1/Complementary External VCO Input for External
VCO Mode.
Power Supply for LDO, Used for PLL1.
True Reference Clock Input 0 of PLL1/RF Synchronization Input with Deterministic Delay.
Complementary Reference Clock Input 0 of PLL1/Complementary RF Synchronization Input with
Deterministic Delay.
Power Supply for Oscillator Output Path.
True Reference Clock Input 2 (Bidirectional Pin) of PLL1/Buffered Output 0 of Oscillator Input.
Complementary Reference Clock Input 2 (Bidirectional Pin) of PLL1/Complementary Buffered
Output 0 of Oscillator Input.
True Buffered Output 1 of Oscillator Input.
Complementary Buffered Output 1 of Oscillator Input.
LDO Bypass, Connect a 4.7 µF capacitor to ground. This pin is the LDO bypass for R2, N2, Phase
Frequency Detector 2 (PFD2), Charge Pump 2 (CP2), and the PLL2 loop filter.
True Feedback Input to PLL1. This pin is a reference input to PLL2.
Complementary Feedback Input to PLL1. This pin is a reference input to PLL2.
LDO Bypass. Connect a 4.7 µF capacitor to ground. This pin is the LDO bypass for the VCXO buffer
and frequency doubler oscillator output divider.
PLL2 Charge Pump Output.
Power Supply for LDO for PLL2.
Programmable General-Purpose Input/Output 2.
True Clock Output Channel 9. Default SYSREF profile.
Complementary Clock Output Channel 9. Default SYSREF profile.
True Clock Output Channel 8. Default DCLK profile.
Complementary Clock Output Channel 8. Default DCLK profile.
Power Supply for Clock Group 3 (North)—Channel 8, Channel 9, Channel 10, and Channel 11. See
the Clock Grouping, Skew, and Crosstalk section.
True Clock Output Channel 10. Default DCLK profile.
Complementary Clock Output Channel 10. Default DCLK profile.
True Clock Output Channel 11. Default SYSREF profile.
Complementary Clock Output Channel 11. Default SYSREF profile.
Programmable General-Purpose Input/Output 3. Sleep input by default.
Programmable General-Purpose Input/Output 4. Pulse generator request by default.
True Clock Output Channel 13. Default SYSREF profile.
Rev. B | Page 15 of 72