HMC7044 Datasheet, PDF (38/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
REFERENCE BUFFER DETAILS
Input Termination Network—Common for All Input
Buffers
The four reference input buffers to PLL1, as well as the VCXO
input buffer, share similar architecture and control features. The
input termination network is configurable to 100 Ω, 200 Ω, and
2 kΩ differentially. It is typically ac-coupled on the board, and
uses the on-chip resistive divider to set the internal common-
mode voltage, VCM, to 2.1 V.
By closing the 50 Ω termination switch (see Figure 48), the
network also serves as the termination system for an LVPECL
driver. Although the input termination network for the four
PLL1 reference buffers and the VCXO input buffer is identical,
the buffer behind the network is different.
2.8V
4kΩ
50Ω,
100Ω,
1kΩ
5kΩ
1pF
50Ω,
100Ω,
50Ω
1kΩ
Figure 48. On-Chip Termination Network for VCXO and Reference Buffers
PLL1 Reference Buffer Stages
The PLL1 reference buffers use a CMOS input stage, are capable
of a wide common-mode input range (0.4 V to 2.4 V), and have
hysteresis to support reliable LOS detection. These buffers are
designed to be driven reliably with an input swing of >375 mV p-p
diff (the half swing point of the LVDS standard), and support up to
800 MHz operation. For signal swings that are below 375 mV p-p
diff, the hysteresis of the buffer can engage and shut down the
signal to the internal reference paths. The exact input hysteresis
threshold varies as a function of common-mode level and input
frequency, but generally ranges from about 75 mV p-p diff to
300 mV p-p diff.
VCXO Buffer Stage
The VCXO input buffer is implemented with a bipolar input
stage to meet the stringent noise requirements of PLL2. Its
common-mode input range is tighter and, if set externally, must
be kept between 1.6 V and 2.4 V. This buffer does not have
hysteresis and is functional down to very low signal levels.
Although the buffer remains functional down to these low
signal levels, for optimal performance, keep the input power
greater than −4 dBm when driven single-ended, or −7 dBm per
side when driven differentially.
Recommendations for Normal Use
For both styles of buffer, unless there are extenuating circum-
stances in the application, use the 100 Ω differential termination to
control reflections, use the on-chip dc bias network to set the
common-mode level, and externally ac couple the input signals.
Do not use receiver side dc termination of the LVPECL signal.
Single-Ended Operation
The buffers support single-ended signals with a slightly reduced
input sensitivity and bandwidth. If driving these buffers single-
ended, ac couple the unused section of the buffer to ground at
the input of the die.
Maximum Signal Swing Considerations
The internal supplies to these buffers are regulated from 3.3 V
to 2.8 V using on-chip regulation. With very high power
references, the signal swing can be enough to drive the signal
above the 2.8 V rail. The ESD network and parasitic diodes are
generally able to shunt the excess power, and protect the
internal circuits even above 13 dBm. Nevertheless, to protect
from latch-up concerns, the signals on reference inputs must
not exceed the 2.8 V internal supply. For a 2.1 V common-
mode, 50 Ω single-ended source, this 2.8 V limit allows
~700 mV of amplitude, or 6 dBm of maximum reference power.
TYPICAL PROGRAMMING SEQUENCE
To initialize the HMC7044 to an operational state, use the
following programming procedure:
1. Connect the HMC7044 to the rated power supplies. No
specific power supply sequencing is necessary.
2. Release the hardware reset by switching from Logic 1 to
Logic 0) when all supplies are stable.
3. Load the configuration updates (provided by Analog
Devices) to specific registers (see Table 74).
4. Program PLL2. Select the VCO range (high or low). Then
program the dividers (R2, N2, and reference doubler).
5. Program PLL1. Set the lock detect timer threshold based
on the PLL1 BW of the user system. Set the LCM, R1, and
N1 divider setpoints. Enable the reference and VCXO
input buffer terminations.
6. Program the SYSREF timer. Set the divide ratio (a submultiple
of the lower output channel frequency). Set the pulse
generator mode configuration, for example, selecting level
sensitive option and the number of pulses desired.
7. Program the output channels. Set the output buffer modes
(for example, LVPECL, CML, and LVDS). Set the divide
ratio, channel start-up mode, coarse/analog delays, and
performance modes.
8. Wait until the VCO peak detector loop has stabilized
(~10 ms after Step 4).
9. Ensure that the references are provided to PLL1 and the
VCXO is powered.
10. Issue a software restart to reset the system and initiate
calibration. Toggle the restart dividers/FSMs bit to 1 and
then back to 0.
11. PLL1 starts to lock in parallel with PLL2 going through its
calibration and lock procedure. Wait for PLL2 to be locked
(takes ~50 μs in typical configurations).
12. Confirm that PLL2 is locked by checking the PLL2 lock
detect bit.
Rev. B | Page 38 of 72