HMC7044 Datasheet, PDF (58/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
Table 50. PLL2 Charge Pump Control
Address Bits Bit Name
Settings
0x0037 [7:4] Reserved
[3:0] PLL2 CP
Current[3:0]
Description
Reserved.
These 4 bits set the magnitude of PLL2 charge pump current. Granularity is
~160 µA with full magnitude of ~2560 µA.
Access
RW
Table 51. PLL2 PFD Control
Address Bits Bit Name
0x0038 [7:5] Reserved
4 PLL2 PFD up enable
3 PLL2 PFD down
enable
2 PLL2 PFD up force
1 PLL2 PFD down
force
0 PLL2 PFD polarity
Settings
Description
Reserved
Enable PLL2 PFD up
Enable PLL2 PFD down
Force PLL2 charge pump up; do not assert simultaneously with PLL2 PFD
down force
Force PLL2 charge pump down; do not assert simultaneously with PLL2
PFD up force
Select PFD polarity
0
Positive
1
Negative
Access
RW
Table 52. OSCOUTx/OSCOUTx Path Control
Address Bits Bit Name
Settings
0x0039 [7:3] Reserved
[2:1] OSCOUTx/OSCOUTx
Divider[1:0]
00
01
10
11
0 OSCOUTx/OSCOUTx
path enable
Description
Reserved
Oscillator output divider ratio
Divided by 1
Divided by 2
Divided by 4
Divided by 8
Enable the oscillator output path (divider and the internal path except
driver)
Access
RW
Table 53. OSCOUTx/OSCOUTx Driver Control
Address
Bits Bit Name
0x003A,
0x003B
[7:6] Reserved
[5:4] OSCOUTx/OSCOUTx Driver Mode[1:0]
[3] Reserved
[2:1] OSCOUTx/OSCOUTx Driver
Impedance[1:0]
0
1 _{X means don’t care.}
OSCOUTx/OSCOUTx driver enable
Settings¹
00
01
10
11
00
01
10
11
Description
Reserved
Oscillator output driver mode selection
CML mode
LVPECL mode
LVDS mode
CMOS mode
Reserved
Oscillator output driver impedance selection for
CML mode
Internal resistor disable
Internal 100 Ω resistor enable per output pin
Reserved
Internal 50 Ω resistor enable per output pin
Enable oscillator driver
Access
RW
Rev. B | Page 58 of 72