HMC7044 Datasheet, PDF (20/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
700
600
500
400
–40°C
300
+25°C
+85°C
200
100
0
DELAY SETTING
Figure 21. Analog Delay vs. Delay Setting over Temperature, LVPECL at
3072 MHz with Digital Delay = 0
30
–40°C
+25°C
+85°C
25
20
15
10
DELAY STEP
Figure 22. Analog Delay Step Size vs Delay Step over Temperature, LVPECL
at 3072 MHz with Digital Delay = 1
800
700
600
500
400
–40°C
+25°C
300
+85°C
200
100
0
DELAY SETTING
Figure 23. Analog Delay vs. Delay Setting over Temperature, LVPECL at
3072 MHz with Digital Delay = 1
Data Sheet
0.6
CLKOUT0
2.5
CLKOUT2
VALID PHASE ALARM
0.4
2.0
0.2
1.5
0
1.0
–0.2
0.5
–0.4
0
–0.6
0
–0.5
200
400
600
800
1000
TIME (ns)
Figure 24. Output Channel Synchronization Before and After Rephase
0.6
2.5
0.4
2.0
CLKOUT0
CLKOUT2
VALID PHASE ALARM
0.2
1.5
0
1.0
–0.2
0.5
–0.4
0
–0.6
330
335
340
345
TIME (ns)
–0.5
350
Figure 25. Output Channel Synchronization Before Rephase
0.6
2.5
0.4
2.0
0.2
1.5
0
1.0
–0.2
0.5
–0.4
0
–0.6
695
CLKOUT0 VALID PHASE ALARM
CLKOUT2
700
705
710
–0.5
715
TIME (ns)
Figure 26. Output Channel Synchronization After Rephase
Rev. B | Page 20 of 72