HMC7044 Datasheet, PDF (18/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
160
140
120
100
80
60
40
20
0
100
JITTER WIDE LOOP
JITTER NARROW LOOP
600 1100 1600 2100 2600 3100 3600
FREQUENCY (MHz)
Figure 9. 12 kHz to 20 MHz Jitter vs. Frequency, Wide Loop and Narrow
Loop at Common Output Frequencies
–90
–95
–100
8
–105
–110
–115
1
–120
8: 100Hz, –99.8dBc/Hz
1: 1kHz, –111.1dBc/Hz
2: 10kHz, –119.8dBc/Hz
3: 100kHz, –125.2dBc/Hz
7: 300kHz, –126.9dBc/Hz
4: 1MHz, –131.3Bc/Hz
5: 10MHz, –153.1dBc/Hz
6: 32.8MHz, –156.3dBc/Hz
x: START 12kHz
STOP 20MHz
CENTER 10MHz
SPAN 20MHz
2
–125
–130
3
7
–135
4
–140 _NOISE:
–145
ANALYSIS RANGE X: BAND MARKER
ANALYSIS RANGE Y: BAND MARKER
–150
INTG NOISE: –66.4dBc/20MHz
RMS NOISE: 678µrad
–155
.039°
RMS JITTER: 44fs
RESIDUAL FM: 1.5kHz
–160
100
1k
10k
100k
1M
FREQUENCY (Hz)
6
5
10M
Figure 10. Phase Noise, CLKOUTx/CLKOUTx = 2457.6 MHz, Optimized for Best
Integrated Jitter (12 kHz to 20 MHz)
100
90
80
2865.72MHz
70
3511.86MHz
60
50
40
2115.38MHz
30
2627.755 MHz
20
10
CAP = 0 LOW VCO
CAP = 0 HIGH VCO
CAP = 31 LOW VCO
CAP = 31 HIGH VCO
0
0
0.5
1.0
1.5
2.0
2.5
3.0
VCO V_TUNE (V)
Figure 11. VCO Gain (KVCO) vs. VCO VTUNE
Data Sheet
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
100M
LOW VCO –40°C
LOW VCO +25°C
LOW VCO +85°C
HIGH VCO –40°C
HIGH VCO +25°C
HIGH VCO +85°C
FREQUENCY (MHz)
Figure 12. VCO VTUNE vs. Frequency
LVPECL
CML100 HIGH
CML100 LOW
LVDS HIGH
CMOS (NOT IN
DIFFERENTIAL MODE)
1G
3G
FREQUENCY (Hz)
Figure 13. Differential Output Voltage vs. Frequency at Different Modes
2.25
2.10
1.95
1.80
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
0.45
0.30
0.15
0
1.0
LVPECL
CML100 HIGH
CML100 LOW
LVDS HIGH
1.5
2.0
2.5
3.0
3.5
FREQUENCY (GHz)
Figure 14. Differential Output Voltage vs. Frequency at Different Modes
Rev. B | Page 18 of 72