HMC7044 Datasheet, PDF (42/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
SERIAL CONTROL PORT
SERIAL PORT INTERFACE (SPI) CONTROL
The HMC7044 can be controlled via the SPI using 24-bit
registers and three pins: serial port enable (SLEN) serial data
input/output (SDATA), and serial clock (SCLK).
The 24-bit register, shown in Table 24, consists of the following:
• 1-bit read/write command
• 2-bit multibyte field (W1, W0)
• 13-bit address field (A12 to A0)
• 8-bit data field (D7 to D0)
Table 24. SPI Bit Map
MSB
Bit 23 Bit 22 Bit 21
R/W
W1
W0
Bits[20:8]
A12 to A0
LSB
Bits[7:0]
D7 to D0
Typical Read Cycle
A typical read cycle is shown in Figure 48 and occurs as follows:
1. The master (host) asserts both SLEN and SDATA to
indicate a read, followed by a rising edge SCLK. The slave
(HMC7044) reads SDATA on the first rising edge of SCLK
after SLEN. Setting SDATA high initiates a read.
2. The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7044 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
3. The host places the 13-bit address field (A12 to A0) MSB
first on SDATA on the next 13 falling edges of SCLK. The
HMC7044 registers the 13-bit address field (MSB first) on
SDATA over the next 13 rising edges of SCLK.
4. The host registers the 8-bit data on the next eight rising
edges of SCLK. The HMC7044 places 8-bit data (D7 to D0)
MSB first on the next eight falling edges of SCLK.
5. Deassertion of SLEN completes the register read cycle.
Typical Write Cycle
A typical write cycle is shown in Figure 49, and occurs as
follows:
1. The master (host) asserts both SLEN and SDATA to
indicate a read, followed by a rising edge SCLK. The slave
(HMC7044) reads SDIO on the first rising edge of SCLK
after SLEN. Setting SDATA low initiates a write.
2. The host places the 2-bit multibyte field to be written to
low (0) on the next two falling edges of SCLK. The
HMC7044 registers the 2-bit multibyte field on the next
two rising edges of SCLK.
3. The host places the13-bit address field (A12 to A0), MSB
first on SDATA on the next 13 falling edges of SCLK. The
HMC7044 registers the 13-bit address field (MSB first) on
SDIO over the next 13 rising edges of SCLK.
4. The host places the 8-bit data (D7 to D0) MSB first on the
next eight falling edges of SCLK. The HMC7044 register
the 8-bit data (D7 to D0) MSB first on the next eight rising
edges of SCLK.
5. The final rising edge of SCLK performs the internal data
transfer into the register file, updating the configuration of
the device.
6. Deassertion of SLEN completes the register write cycle.
SCLK
1
2
3
4
5 16 17 18 24
SDATA ^{X READ W1 W0 A12 A11 A0 D7 D6 D0}
SLEN
SCLK
Figure 49. SPI Timing Diagram, Read Operation
1
2
3
4
5 16 17 18 24
WRITE
SDATA ^X
W1 W0 A12 A11 A0 D7 D6 D0
SLEN
Figure 50. SPI Timing Diagram, Write Operation
Rev. B | Page 42 of 72