HMC7044 Datasheet, PDF (55/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Table 35. PLL1 Holdover Exit Control
Address Bits Bit Name
0x0016 [7:4] Reserved
[3:2] Holdover Exit Action[1:0]
[1:0] Holdover Exit Criteria[1:0]
1 _{X means don’t care.}
Settings
00
01
10
11
X0¹
01
11
Description
Reserved
Action the PLL1 FSM takes as it exits holdover mode.
Reset dividers.
Do nothing.
Do nothing.
DAC assist.
Criteria the PLL1 FSM uses to exit holdover mode.
Exit holdover when LOS is gone.
Exit holdover when phase error = 0.
Exit holder immediately.
Access
RW
Table 36. PLL1 Holdover DAC/ADC Control
Address Bits Bit Name
Settings
0x0017 7 Reserved
[6:0] Holdover DAC
Value[6:0]
0x0018
[7:4] Reserved
3 ADC tracking
disable
2 Force DAC to
holdover in quick
mode
[1:0] Holdover BW
Reduction[1:0]
Description
Reserved
In holdover mode, if ADC tracking disable is set 1, the holdover DAC control
value is set to this value (regarded as an unsigned integer value); otherwise,
the holdover average DAC value is summed by this value (regarded as twos
complement coded signed integer value)
Reserved
Disable ADC tracking; use DAC hold word
Force DAC control value from DAC current value to computed DAC holdover
value immediately, not gradually
Reduce tracking BW
Access
RW
RW
Table 37. PLL1 LOS Mode Control
Address Bits Bit Name
0x0019 [7:2] Reserved
1 LOS bypass input
prescaler
0 LOS uses VCXO prescaler
Settings
Description
Reserved
Bypass LCM R divider cascade; the R1 input is the selected
CLKINx/CLKINx input
For very low PFD rates; cascades VCXO LCM divider after N1
Access
RW
Table 38. PLL1 Charge Pump Control
Address
Bits
Bit Name
0x001A
[7:4]
Reserved
[3:0]
PLL1 CP Current[3:0]
Settings
Description
Reserved
PLL1 charge pump current
Access
RW
Rev. B | Page 55 of 72