HMC7044 Datasheet, PDF (32/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
The HMC7044 output network also supports the following
recommended features, which are sometimes critical in user
applications:
• Deterministic synchronization of the output channels with
respect to an external signal, which allows multichip
synchronization and clean expansion to larger systems
• Pulse generator behavior to temporarily generate a
synchronization pulse stream at user request
• Flexibility to define unused JESD204B SYSREF and DCLK
channels for other purposes
• Glitchless phase control of signals relative to each other
• 50% duty cycle clocks with odd division ratios
• Multimode output buffers with a variety of swings and
termination options
• Skew between all channels that is much less than a DCLK
period
• Adjustable performance vs. power consumption for less
sensitive clock channels
• Flexibility to use an external VCO for very high
performance application requirements
SYSREF INPUT NETWORK
SYNC FROM PLL2 N DIVIDER
(DUE TO SYNC PIN EVENT)
Data Sheet
Each of the 14 output channels are logically identical. The only
distinction between the SYSREF and DCLK channels is in the
SPI configuration and in how they are used. Each channel
contains independent dividers, phase adjustment, and analog
delay circuits. This combination provides the ultimate flexibility,
cleanly accommodating nonJESD204B devices in the system.
In addition to the 14 output channel dividers, there is an internal
SYSREF timer that continually operates, and the synchronization
of the output channel dividers occurs deterministically with respect
to this timer, which can be rephased externally by the user.
The pulse generator functionality of the JESD204B standard
involves temporarily generating SYSREF output pulses, with
appropriate phasing, to downstream devices. The centralized
SYSREF timer and its associated SYNC/pulse generator control
manage the process of enabling the intended SYSREF channels,
phasing them, and then disabling them for signal integrity and
power saving advantages.
RF SYNC
DQ
RESET
VCO PATH
SYSREF
TIMER
SYNC/
PULSE GENERATOR
CONTROL
PULSE GENERATOR REQUEST (FROM SPI, GPI, OR SYNC PIN)
SYNC REQUEST (FROM SPI OR GPI)
SYNC_FSM_STATE
OUTPUT CHANNEL × 14
LEAF
CONTROLLER
CLOCK
GATING
DIVIDER
DIGITAL DELAY
AND RETIME
Figure 44. Clock Output Network Simplified Diagram
Rev. B | Page 32 of 72