HMC7044 Datasheet, PDF (65/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Address Bits Bit Name
0x008F [7:4] PLL2 Autotune FSM
State[3:0]
[3:0] PLL2 SYNC FSM State[3:0]
0x0090 [7:0] Reserved
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
0000
0100
0110
0111
1110
1100
Description
Autotune FSM state
Idle
Startup
Startup
Reset
Reset
Reset
Measure
Wait
Wait
Update loop to state 18 times
Round
Finish
PLL2 sync carry FSM state
Idle
Power up Section A of the FSM
Power up Section B of the FSM
Sending to N2
Power down Section A of the FSM
Power down Section B of the FSM
Reserved
SYSREF Status Register (Register 0x0091)
Table 73. SYSREF Status Register
Address Bits Bit Name
0x0091 [7:5] Reserved
4 Channel outputs
FSM busy
[3:0] SYSREF FSM
State[3:0]
Settings
0000
0010
0100
0101
0110
1010
1011
1100
1101
1110
1111
Description
Reserved.
One of clock outputs FSM requested clock, and it is running.
Indicates the current step of the SYSREF reseed process. Note that the three
different progressions are caused by different trigger events (reseed, pulse
generator, reserved).
Reset.
Done.
Get ready.
Get ready.
Get ready.
Running (pulse generator).
Start.
Power up.
Power up.
Power up.
Clear reset.
Access
R
R
Access
R
Rev. B | Page 65 of 72