HMC7044 Datasheet, PDF (64/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
PLL1 Status Registers (Register 0x0082 to Register 0x0087)
Table 71. PLL1 Status Registers
Address Bits Bit Name
0x0082 7 Reserved
[6:5] PLL1 Best Clock[1:0]
[4:3] PLL1 Active CLKINx/
CLKINx[1:0]
[2:0] PLL1 FSM State[2:0]
0x0083
0x0084
0x0085
7 Reserved
[6:0] Holdover DAC Averaged
Value[6:0]
7 Holdover comparator value
[6:0] Holdover DAC Current
Value[6:0]
[7:4] Reserved
3 PLL1 active CLKINx/CLKINx
LOS
2 PLL1 VCXO status
1 PLL1 holdover ADC status
0x0086
0x0087
0 PLL1 holdover ADC input
range status
[7:5] Reserved
[4:3] PLL1 Holdover Exit
Phase[1:0]
[2:0] Reserved
[7:0] Reserved
Settings
Description
Reserved
Indicates which clock the LOS/priority encoder prefers if automode
reference switching is used
Indicates which CLKINx/CLKINx input is currently in use
Access
R
Sets the state PLL1 is in
000
Reset
001
Acquisition
010
Locked
011
Invalid
100
Holdover
101
DAC assisted holdover exit
Reserved
R
Average DAC code
Holdover comparator output value (DAC output vs. PLL1 VTUNE)
R
Current DAC code
Reserved
R
LOS of the currently active reference
Indicates whether any of the enabled references appears to run
faster than the VCXO
0
ADC is acquiring
1
PLL1 VTUNE is moving quickly
0
PLL1 VTUNE is in range
1
PLL1 VTUNE is out of range
Reserved
R
The phase of the PLL1 holdover exit
Reserved
Reserved
R
PLL2 Status Registers (Register 0x008C to Register 0x0090)
Table 72. PLL2 Status Registers
Address Bits Bit Name
0x008C [7:0] PLL2 autotune value
0x008D
0x008E
[7:0] PLL2 Autotune Signed
Error[7:0] (LSB)
7 PLL2 autotune status
6 PLL2 autotune error sign
[5:0] PLL2 Autotune Signed
Error[13:8] (MSB)
Settings
Description
After autotune, this word is populated with the selected capacitor
bank of the VCO
14-bit PLL2 VTUNE error count, LSB
1
Autotune busy
0
Done/not working
Sign of PLL2 autotune error
0
Positive
1
Negative
14-bit PLL2 VTUNE error count, MSB
Access
R
R
R
Rev. B | Page 64 of 72