HMC7044 Datasheet, PDF (54/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
Table 30. Global Clear Alarms
Address Bits Bit Name
0x0006 [7:1] Reserved
0
Clear alarms
Settings
Description
Reserved
Clear latched alarms
Access
RW
Table 31. Global Miscellaneous Control
Address Bits Bit Name
0x0007 [7:0] Reserved
0x0008 [7:0] Reserved (Scratchpad)
0x0009 [7:1] Reserved
0
Disable SYNC at lock
Settings
0
1
Description
Reserved.
Reserved. The user can write/read to this register to confirm I/Os to the
HMC7044. This register does not affect device operation.
Reserved.
PLL2 sends a sync event up N2 when lock is achieved.
This feature is disabled and SYNC is not internally generated on PLL2
lock.
Access
RW
RW
RW
PLL1 (Register 0x000A to Register 0x002A)
Table 32. CLKINx/CLKINx and OSCIN/OSCIN Input Buffer Control
Address
Bits Bit Name
0x000A, 0x000B, 0x000C, 0x000D, 0x000E [7:5] Reserved
[4:1] Input Buffer Mode[3:0]
0
Buffer enable
Settings
Bit 0
Bit 1
Bit 2
Bit 3
Description
Reserved
Input buffer control
Enable internal 100 Ω termination
Enable ac coupling input mode
Enable LVPECL input mode
Enable high-Z input mode
Enable input buffer
Access
RW
Table 33. PLL1 Reference Priority Control
Address Bits Bit Name
0x0014 [7:6] Fourth Priority CLKINx/CLKINx Input[1:0]
[5:4] Third Priority CLKINx/CLKINx Input[1:0]
[3:2] Second Priority CLKINx/CLKINx Input[1:0]
[1:0] First Priority CLKINx/CLKINx Input[1:0]
Settings
Description
If third choice clock is not available, use the fourth
choice clock
If second choice clock is not available, use the third
choice clock
If the first choice clock is not available, use the
second choice clock
This is the first choice clock
Access
RW
Table 34. PLL1 Loss of Signal (LOS) Control
Address Bits Bit Name
Settings
0x0015 [7:3] Reserved
[2:0] LOS Validation
Timer[2:0]
000
001
010
011
100
101
110
111
Description
Reserved.
LCM cycles of LOS hysteresis. This is the number of LCM cycles to wait before
exiting LOS state when the reference input becomes valid again.¹
None.
2 cycles.
4 cycles.
8 cycles.
16 cycles.
32 cycles.
64 cycles.
128 cycles.
Access
RW
1 _{The LOS revalidation takes between two and three times this number of cycles. The LOS revalidation ambiguity is dependent on whether another channel is in LOS.}
Rev. B | Page 54 of 72