HMC7044 Datasheet, PDF (3/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
SPECIFICATIONS
Unless otherwise noted, fVCXO = 122.88 MHz single-ended; CLKIN0/CLKIN0, CLKIN1/CLKIN1, CLKIN2/CLKIN2, and CLKIN3/CLKIN3
differential at 122.88 MHz; fVCO = 2949.12 MHz; doubler is on; typical value is given for VCC = 3.3 V; and TA = 25°C. Minimum and maximum
values are given over the full VCC and TA (−40°C to +85°C) variation, as listed in Table 1. Note that multifunction pins, such as
CLKIN0/RFSYNCIN, are referred to either by the entire pin name or by a single function of the pin, for example, CLKIN0, when only
that function is relevant.
CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE, VCC
VCC1_VCO
VCC2_OUT
VCC3_SYSREF
VCC4_OUT
VCC5_PLL1
VCC6_OSCOUT
VCC7_PLL2
VCC8_OUT
VCC9_OUT
TEMPERATURE
Ambient Temperature Range, TA
Min Typ Max Unit Test Conditions/Comments
3.135 3.3 3.465 V
3.135 3.3 3.465 V
3.135 3.3 3.465 V
3.135 3.3 3.465 V
3.135 3.3
3.135 3.3
3.135 3.3
3.135 3.3
3.465 V
3.465 V
3.465 V
3.465 V
3.135 3.3 3.465 V
3.3 V ± 5%, supply voltage for VCO and VCO distribution
3.3 V ± 5%, supply voltage for Output Channel 2 and Output
Channel 3
3.3 V ± 5%, supply voltage for common SYSREF divider
3.3 V ± 5%, supply voltage for Output Channel 4, Output
Channel 5, Output Channel 6, Output Channel 7
3.3 V ± 5%, supply voltage for the LDO used in PLL1
3.3 V ± 5%, supply voltage for oscillator output path
3.3 V ± 5%, supply voltage for the LDO used in PLL2
3.3 V ± 5%, supply voltage for Output Channel 8, Output
Channel 9, Output Channel 10, and Output Channel 11
3.3 V ± 5%, supply voltage for Output Channel 0, Output
Channel 1, Output Channel 12, and Output Channel 13
−40 +25 +85 °C
SUPPLY CURRENT
For detailed test conditions, see Table 22 and Table 23.
Table 2.
Parameter^{1, 2}
Min Typ
CURRENT CONSUMPTION³
VCC1_VCO
157
VCC2_OUT⁴
65
VCC3_SYSREF
12
VCC4_OUT⁴
78
VCC5_PLL1
39
VCC6_OSCOUT
0
VCC7_PLL2
46
VCC8_OUT⁴
124
VCC9_OUT⁴
65
Total Current
586
Max Unit Test Conditions/Comments
225 mA
250 mA Typical value is given at TA = 25°C with two LVDS clocks at divide by 8
37 mA
500 mA Typical value is given at 25°C with two LVPECL high performance clocks,
fundamental frequency of internal VCO (fO), 2 SYSREF clocks (off )
125 mA
80 mA
80 mA
500 mA Typical value is given at 25°C with two LVPECL high performance clocks at
divide by 2, 2 SYSREF clocks (off )
500 mA Typical value is given at 25°C with two LVDS clocks at divide by 8, 2 SYSREF
clocks (off )
mA
1_{Maximum values are guaranteed by design and characterization.}
2 _{Currents include LVPECL termination currents.}
3 _{Maximum values are for all circuits enabled in their worst case power consumption mode, PVT variations, and accounting for peak current draw during temporary}
synchronization events.
4 _{Typical specification applies to a normal usage profile (Profile 1 in Table 23), where PLL1 and PLL2 are locked, but very low duty cycle currents (sync events) and some}
optional features are disabled. This specification assumes output configurations as described in the test conditions/comments column.
Rev. B | Page 3 of 72