HMC7044 Datasheet, PDF (5/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
PLL1 CHARACTERISTICS
Table 4.
Parameter
Min
Typ
Max
PLL1 REFERENCE INPUTS
(CLKIN0/CLKIN0, CLKIN1/CLKIN1,
CLKIN2/CLKIN2, CLKIN3/CLKIN3)
Reliable Signal Swing
Differential
0.375
1.4
Single-Ended¹
0.375
1.4
Common-Mode Range
0.4
2.4
Input Impedance
Return Loss
PLL1 REFERENCE DIVIDER
8-Bit Lowest Common Multiple
(LCM) Dividers
16-Bit R Divider (R1)
PLL1 FEEDBACK DIVIDER
16-Bit N Divider (N1)
PLL1 FREQUENCY LIMITATIONS
PLL1 REF Input Frequency (fREF)
100 to 2000
−12
1
255
1
65,535
1
65,535
0.00015
800
Digital LOS/LCM Frequency (fLCM) 0.00015
123
PD1 Frequency (fPD1)
0.00015
50
PLL1 CHARGE PUMP
Charge Pump Current Range (ICP1)
120 to 1920
ICP1 Variation over Process Voltage
Temperature (PVT)
Source/Sink Current Mismatch
Charge Pump Current Step Size
Charge Pump Compliance Range¹
PLL1 NOISE PROFILE¹
Floor Figure of Merit (FOM)
Flicker FOM
Flicker Noise
Noise Floor
Total Phase Noise (Unfiltered)
PLL1 BANDWIDTH AND
ACQUISITION TIMES¹
Supported Loop Bandwidths
(PLL1_BW)⁵
PLL1 Slew Time⁶
PLL1 Linear Acquisition Time
±15
2
120
0.4 to 2.5
0.1 to 2.7
−222
−252
Determined by formula²
Determined by formula³
Determined by formula⁴
fLCM/2²⁵
fPD1/10
5/PLL1_BW
N1/
fDELTA_VCXO
PLL1 Phase Error at PD1
Invalidates Lock
PLL1 Lock Detect Timer Period
(tLKD)⁷
±2.9
4 to 2²⁶
Unit
Test Conditions/Comments
V p-p
V p-p
V
Ω
dB
Differential, keep signal at reference input pin
<2.8 V, measured at 800 MHz
<250 MHz; keep signal at reference input pin
<2.8 V
If user supplied, on-chip VCM is approximately
2.1 V
User selectable; differential
When terminated with 100 Ω differentially
MHz
Minimum specification set by Phase Detector 1
(PD1) low limit
MHz
Typically run at about 38.4 MHz
MHz
Minimum specification = VCXO minimum
frequency ÷ 65,535; 9.76 MHz typical
μA
ICP1 from 0 to 15, VCXO control voltage (VTUNE) =
1.4 V
%
VTUNE = 1.4 V
%
Source/sink mismatch at 1.4 V
μA
V
ICP variation less than 10%
V
Maintain lock in test environment
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Normalized to 1 Hz
Normalized to 1 Hz
At fOUT, fOFFSET
At fOUT, fPD1
Hz
Typically PLL1 low BW is set by the application
and ranges between 5 Hz and 2 kHz
sec
N1 = 10 (typical) and fDELTA_VCXO = 10 kHz (typical)
results in 1 ms of slew time
sec
When VCXO has stopped slewing to steady
state (within 5°)
ns
tLCM
User-selectable low phase error counts to
declare lock
Rev. B | Page 5 of 72