HMC7044 Datasheet, PDF (60/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
Address
Bits Bit Name
1 GPOx mode
0 GPOx enable
Settings
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
0
1
Description
PLL1 holdover exit phase, Bit 0
PLL1 holdover exit phase, Bit 1
Channel outputs FSM busy
SYSREF FSM state, Bit 0
SYSREF FSM state, Bit 1
SYSREF FSM state, Bit 2
SYSREF FSM state, Bit 3
Force Logic 1 to GPO
Force Logic 0 to GPO
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PLL1 holdover DAC averaged value, Bit 0
PLL1 holdover DAC averaged value, Bit 1
PLL1 holdover DAC averaged value, Bit 2
PLL1 holdover DAC averaged value, Bit 3
PLL1 holdover DAC current value, Bit 0
PLL1 holdover DAC current value, Bit 1
PLL1 holdover DAC current value, Bit 2
PLL1 holdover DAC current value, Bit 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Holdover comparator status
Pulse generator request status signal
Reserved
Selects the mode of GPOx driver
Open-drain mode
CMOS mode
GPOx driver enable
Access
Table 56. SDATA Control
Address
Bits
0x0054
[7:2]
1
Bit Name
Reserved
SDATA mode
0
SDATA enable
Settings
0
1
Description
Reserved
Selects the mode of SDATA driver
Open-drain mode
CMOS mode
SDATA driver enable
Rev. B | Page 60 of 72
Access
RW