HMC7044 Datasheet, PDF (59/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
GPIO/SDATA Control (Register 0x0046 to Register 0x0054)
Table 54. GPIx Control
Address
Bits
0x0046, 0x0047,
[7:5]
0x0048, 0x0049
[4:1]
0
Bit Name
Reserved
GPIx Selection[3:0]
GPIx enable
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Reserved.
Select the GPIx functionality.
Reserved.
Force PLL1 to holdover.
Select PLL1 reference manually, Bit 1.
Select PLL1 reference manually, Bit 0.
Put the chip into sleep mode.
Issue a mute.
Select the internal VCO type manually.
Select high performance mode for PLL2 and the internal VCO.
Issue a pulse generator request.
Issue a reseed request.
Issue a restart request.
Force the chip into fanout mode.
Reserved.
Issue a slip request
Reserved.
Reserved.
GPIx function enable. Before changing the function of the pin,
disable it first, and then reenable it after the function change.¹
1 _{Note that it is possible to have a GPIOx pin configured as both an output and an input.}
Access
RW
Table 55. GPOx Control
Address
Bits Bit Name
Settings Description
Access
0x0050, 0x0051, 0x0052, 0x0053 [7:2] GPOx Selection[5:0]
Select the GPOx functionality
RW
000000 Alarm signal
000001 SDATA from SPI communication
000010 CLKIN3/CLKIN3 LOS for CLKIN3/CLKIN3 input
000011 CLKIN2/CLKIN2 LOS for CLKIN2/CLKIN2input
000100 CLKIN1/CLKIN1 LOS for CLKIN1/CLKIN1 input
000101 CLKIN0/CLKIN0 LOS for CLKIN0/CLKIN0 input
000110 PLL1 holdover enabled signal from PLL1
000111 Lock detect signal from PLL1
001000 Acquiring lock signal from PLL1
001001 PLL1 near lock acquisition status signal from PLL1
001010 PLL2 lock detect signal from PLL2
001011 SYSREF sync status has not synchronized since reset
001100 Clock outputs phase status
001101 PLL1 and PLL2 lock detect is locked
001110 Sync request status signal
001111 PLL1 active CLKIN0/CLKIN0
010000 PLL1 active CLKIN1/CLKIN1
010001 PLL1 holdover ADC input range status
010010 PLL1 holdover ADC input status
010011 PLL1 VCXO status
010100 PLL1 active CLKINx/CLKINx status
010101 PLL1 FSM state, Bit 0
010110 PLL1 FSM state, Bit 1
010111 PLL1 FSM state, Bit 2
Rev. B | Page 59 of 72