HMC7044 Datasheet, PDF (37/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
Table 20. Supply Pin Clock Grouping by Location
Supply Pin
Location
Clock Group Channel
VCC2_OUT
Southwest
1
2
3
VCC4_OUT
South
2
4
5
3
6
7
VCC8_OUT
North
4
8
9
5
10
11
VCC9_OUT
Northwest
6
12
13
0
0
1
Table 21. Typical Skew and Isolation vs. Distance
Distance
Typical
1 GHz Isolation
Skew (ps) Differential (dB)
Distant Supply Group
±20
90 to 100
Closest Neighbor on
±15
70
Different Supply Group
Shared Supply
±10
60
Same Clock Group
±10
45
Output Buffer Details
Figure 47 shows the clock groups by supply pin location on the
package. With appropriate supply pin bypassing, spurious noise
of the outputs is improved. Table 20 describes how the supply
pins of each of the 14 clock channels are connected within the
seven clock groups. Clock channels that are closest to each
other have the best channel to channel skew performance, but
they also have the lowest isolation from each other. Select
critical signals that require high isolation from each other from
groups with distant supply pin locations. An example of the
expected isolation and channel to channel skew performance of
the HMC7044 at 1 GHz is provided in Table 21.
NORTHWEST
CLKOUT0,
CLKOUT0
SCLKOUT1,
SCLKOUT1
RESET AND SYNC
BGABYP1
LDOBYP2
LDOBYB3
VCC1_VCO
LDOBYP4
LDOBYP5
SCLKOUT3,
SCLKOUT3
CLKOUT2,
CLKOUT2
VCC2_OUT
NORTH
HMC7044
VCC7_PLL2
CPOUT2
LDOBYP7
OSCIN, OSCIN
LDOBYP6
OSCOUT1,
OSCOUT1
CLKIN2/OSCOUT0,
CLKIN2/OSCOUT0
VCC6_OSCOUT
CLKIN0/RFSYNCIN,
CLKIN0/RFSYNCIN
VCC5_PLL1
CLKIN1/FIN,
CLKIN1/FIN
SOUTHWEST
SOUTH
Figure 47. Clock Grouping
SYSREF Valid Interrupt
One of the challenges in a JESD204B system is to control and
minimize the latency from the primary system controller IC,
typically an ASIC or FPGA, to the data converters. To estimate
the correct amount of latency in the system, the designer must
know how long it takes for a master clock generator like the
HMC7044 to provide the correct output phases at each output
channel after receiving the synchronization request. Typically, a
period of time is required on the device to implement the
change requests on the outputs due to internal state machine
cycles, data transfers, and any propagation delays. The SYSREF
valid interrupt is a function to notify the user that the correct
output settings and phase relationships are established, allowing
the user to identify quickly that the desired SYSREF and device
clock states are presented at the outputs of the HMC7044.
The user has the flexibility to assign the SYSREF valid interrupt
to a GPO pin or to use a software flag, set via Register 0x007D,
Bit 2, which the user can poll as necessary. The flag notifies the
user when the system is configured and operating in the desired
state, or conversely when it is not ready.
Rev. B | Page 37 of 72