HMC7044 Datasheet, PDF (47/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Addr.
(Hex)
Register
Name
Bit 7 (MSB)
Clock Distribution Network
0x0064 External VCO
control
0x0065
Analog delay
common
control
Alarm Masks Registers
0x0070 PLL1 alarm
mask control
PLL1 near
lock mask
0x0071 Alarm mask
control
Product ID Registers
0x0078 Product ID
0x0079
0x007A
Alarm Readback Status Registers
0x007B Readback
register
0x007C PLL1 alarm
readback
PLL1 near
lock
0x007D Alarm
readback
0x007E
0x007F
Latched
alarm
readback
Alarm
readback
miscellaneous
PLL1 Status Registers
0x0082 PLL1 status
registers
0x0083
0x0084
0x0085
Reserved
Reserved
Reserved
Holdover
comparator
value
0x0086
0x0087
PLL2 Status Registers
0x008C PLL2 status
0x008D ^registers
0x008E
0x008F
0x0090
PLL2
autotune
status
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Reserved
Reserved
Divide by
2 on
external
VCO
enable
Low
frequency
external
VCO path
Analog
delay low
power
mode
0x00
0x00
PLL1 lock
acquisition
mask
Reserved
PLL1 lock
detect mask
PLL1 holdover
status mask
PLL1 CLKINx/CLKINx LOS Mask[3:0]
Sync request
mask
PLL1 and
PLL2 lock
detect
mask
Clock
outputs
phase
status
mask
SYSREF
sync
status
mask
PLL2 lock
detect
mask
0x00
0x10
Product ID Value[7:0] (LSB)
Product ID Value[15:8] (Mid)
Product ID Value[23:16] (MSB)
0x51
0x16
0x30
PLL1 lock
acquisition
Reserved
PLL2 lock
acquisition
latched
PLL1 lock
detect
PLL1 lock
acquisition
latched
Reserved
PLL1 holdover
status
Sync request
status
PLL1 holdover
latched
CLKINx/CLKINx LOS[3:0]
Alarm
signal
PLL1 and
PLL2 lock
detect
Clock
outputs
phases
status
SYSREF
sync
status
PLL2 lock
detect
CLKINx/CLKINx LOS Latched[3:0]
Reserved
PLL1 Best Clock[1:0]
PLL1 Active
CLKINx/CLKINx[1:0]
PLL1 Holdover DAC Averaged Value[6:0]
PLL1 Holdover DAC Current Value[6:0]
PLL1 FSM State[2:0]
Reserved
Reserved
PLL1
active
CLKINx/
CLKINx
LOS
PLL1 Holdover Exit
Phase[1:0]
Reserved
PLL1
VCXO
status
PLL1
holdover
ADC
status
Reserved
PLL1
holdover
ADC input
range
status
PLL2 autotune value
PLL2 Autotune Signed Error[7:0] (LSB)
PLL2
autotune
error sign
PLL2 Autotune Signed Error[13:8] (MSB)
PLL2 Autotune FSM State[3:0]
PLL2 SYNC FSM State[3:0]
Reserved
Rev. B | Page 47 of 72