HMC7044 Datasheet, PDF (25/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
DUAL PLL OVERVIEW
The HMC7044 uses a cascade of two PLLs, referred to as a dual
loop topology. The term dual loop sometimes refers to other
architectures as well; therefore, always refer to the block diagram
shown in Figure 35 to remove any ambiguity. In this architecture,
the first PLL (PLL1) normally operates as a jitter attenuator. PLL1
locks a clean local VCXO to a relatively noisy reference using a
very narrow loop bandwidth. The loop bandwidth preserves the
average frequency of the reference signal (which is normally
correct), while rejecting the majority of its noise. The second
PLL takes this low noise VCXO and multiplies it up to the VCO
frequency (in the 2 GHz to 3 GHz range) with very little additive
noise. The architecture provides the benefits of an output frequency
locked to an input reference signal, while being insensitive to its
noise profile.
In ICs such as the HMC7044, the VCO is then connected to an
array of output channels, each with an optional RF divider and
phase control. The key feature that distinguishes an IC with
JESD204B support is the ability to ensure that all of the outputs
with their associated dividers have a user defined phase relationship
each and every time, regardless of process, voltage, or temperature.
This ability is necessary to support the JESD204B SERDES
standard for data converters, but it is also an immensely useful
feature in other applications as well, in all forms of arrayed systems
and in many test and measurement scenarios.
COMPONENT BLOCKS—INPUT PLL (PLL1)
PLL1 General Description (Jitter Attenuator)
A variety of local clocks, particularly in synchronous networks,
derive their timing from a remote node in the network. These
reference signals can arrive via a GPS or clock data recovery
(CDR) receiver, or from a variety of other sources. Often, these
derived references are relatively poor quality, in terms of spurious
content, noise, and reliability.
The function of PLL1 is to lock a clean VCXO to the average
frequency of one of these references and feed it to PLL2 to
generate a high quality clock for local use.
HMC7044
In addition, PLL1 monitors its active reference for failure and
smoothly takes appropriate action, switching to a redundant
reference or going into holdover as appropriate. Figure 36 shows
the architecture of PLL1 with a typical frequency configuration.
Jitter Attenuation
For the purpose of jitter attenuation, PLL1 consists of all the
usual components in a PLL: a phase/frequency detector (PFD1),
charge pump (CP1), reference divider (R1), and feedback
divider (N1). The loop filter is external to provide maximum
flexibility, and the loop bandwidth (BW) is normally configured
very narrow (20 Hz to 500 Hz) to filter any jitter and spurious
tones coming in from relatively poor references.
The noise profile of PLL1 is typically dependent on the loop
bandwidth, input reference noise, and the VCXO characteristic.
The inherent noise sources of PLL1 (the PFD, dividers, and
charge pump) are not normally observable in an application,
and are significantly more relaxed compared with PLL2.
Note that the loop filter components on the board are typically
configured to produce a certain loop bandwidth, given a fixed
PFD rate, charge pump current, and VCXO characteristic.
Adjusting any of these parameters from their nominal positions
affects the loop dynamics, which can be to the advantage of the
user (for example, to scale loop BW with charge pump current),
but it must not be performed without an analysis of the stability
of the loop. Analog Devices, Inc., provides a variety of software
tools to design the loop filter and model the effects of any
change in parameters. Contact Analog Devices for the latest
recommendation.
The lock time of PLL1 typically takes the longest duration in the
clock network, and, aside from any nonlinear slewing, takes
approximately 5/PLL1_BW (for example, 5 ms for a 1 kHz loop
BW). Fortunately, there are no requirements that PLL1 must be
locked before proceeding with PLL2, output calibration, and
phasing, which normally allows system configuration to
continue in parallel while PLL1 is settling.
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