HMC7044 Datasheet, PDF (7/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Parameter
HOLDOVER EXIT—FREQUENCY
TRANSIENTS vs. MODE
Peak Frequency Transient
DAC Assisted Release
Min
Typ
2
Max
Unit
Test Conditions/Comments
ppm
Only available if using DAC-based holdover
1 _{Guaranteed by design and characterization.}
2 _{See the PLL1 Noise Calculations section for more information on how to calculate the flicker noise for PLL1.}
3 _{See the PLL1 Noise Calculations section for more information on how to calculate the noise floor for PLL1.}
4 _{See the PLL1 Noise Calculations section for more information on how to calculate the total phase noise (unfiltered) for PLL1.}
5 _{Set by external components. Set the lock detect thresholds (PLL1 Lock Detect Timer[4:0] in Register 0x0028) appropriately in the SPI.}
6 _{Depends on initial phase offset (worst case is proportional to N1) and VCXO excess tuning range available over the target (fDELTA_VCXO). For PFD rates typical of PLL1,}
cycle slipping is normally insignificant.
7 _{tLCM is the least common multiple (LCM) of PLL1 clock input frequencies. The specification is given in multiples of tLCM.}
8 _{If LOS triggers before the PFD edge is normally detected (more likely with high R1 values), the charge pump is more likely to disable before the next invalid}
comparison occurs. Otherwise, the fast tristate circuit disables the charge pump after about 4 ns (8 ns worst case) of phase error.
9 _{tLOSVAL is a register value that is programmable from 1, 2, 4, …, 64 tLCM.}
10 _{If the holdoff timer is used, the finite state machine (FSM) stays in holdover after LOS of the active reference before switching clocks, giving the original clock a chance}
to return.
11 _{tVCXO is the VCXO clock period.}
12 _{See the PLL1 Holdover Exit section.}
13 _{The time required for the phases to intersect is inversely proportional to the holdover frequency error. Note that the frequency error during holdover is expected to}
be much smaller than is available from the tuning range of the VCXO.
14 _{fERR_VCXO is the error frequency of the VCXO.}
PLL2 CHARACTERISTICS
Table 5.
Parameter
Min
PLL2 VCXO INPUT
Recommended Swing
Differential
0.2
Single-Ended (<250 MHz)¹ 0.2
Common-Mode Range
1.6
VCXO Input Slew Rate
300
Input Capacitance
Differential Input Resistance
Return Loss
PLL2 EXTERNAL VCO INPUT
Recommended Input
Power, AC-Coupled
Differential
−6
Single-Ended¹
−6
Return Loss
External VCO Frequency¹
400
400
Common-Mode Range¹
1.6
PLL2 DIVIDERS
12-Bit Reference Divider
1
Range (R2)
16-Bit Feedback Divider
8
Range (N2)
PLL2 FREQUENCY LIMITATIONS
VCXO Frequency (fVCXO)
10
VCXO Duty Cycle
Using Doubler¹
40
Typ
Max
Unit Test Conditions/Comments
1.4
1.4
2.1
2.4
1.5
100 to 1000
−12
V p-p
V p-p
V
mV/ns
pF
Ω
dB
Differential, keep signal at OSCIN and OSCIN pins < 2.8 V
Keep signal at OSCIN and OSCIN pins < 2.8 V
If user supplied, on-chip VCM is approximately 2.1 V
Slew rates as low as 100 mV/ns are functional, but can
degrade the phase noise plateau by about 3 dB
Per side; 3 pF differential
User selectable
When terminated with 100 Ω differential
6
dBm
6
dBm
−12
dB
When terminated with 100 Ω differential
3200
MHz Fundamental mode; if < 1 GHz, set the low frequency
external VCO path bit (Register 0x0064, Bit 0)
6000
MHz Using external VCO ÷ 2
2.1
2.2
V
4095
65,535
500
MHz 122.88 MHz or 155 MHz are typical
60
%
Distortion can lead to a spur at fPD/2 offset, note that
minimum pulse width > 3 ns
Rev. B | Page 7 of 72