HMC7044 Datasheet, PDF (53/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Address Bits
0x0002 [7:3]
2
Bit Name
Reserved
PLL2 autotune trigger
1
Slip request
0
Reserved
Settings
Description
Reserved.
Triggers an autotune if there is an error/issue when the device comes
out of reset.
Requests a slip or multislip event from all divider channels that are
sensitive to slip or multislip commands. The dividers are rising edge
sensitive and take some time to process the request, after which the
phase synchronization alarm is asserted.
Reserved.
Access
RW
Table 28. Global Enable Control
Address Bits Bit Name
0x0003 [7:6] Reserved
5 RF reseeder enable
[4:3] VCO Selection[1:0]
0x0004
2 SYSREF timer enable
1 PLL2 enable
0 PLL1 enable
7 Reserved
[6:0] Seven Pairs of 14
Channel Outputs
Enable[6:0]
Settings
00
01
10
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Description
Reserved
Enable RF reseed for SYSREF
Internal disabled/external
High
Low
Enable internal SYSREF time reference
Master analog enable to PLL2
Master analog enable to PLL1
Reserved
Enable Channel 0 and Channel 1
Enable Channel 2 and Channel 3
Enable Channel 4 and Channel 5
Enable Channel 6 and Channel 7
Enable Channel 8 and Channel 9
Enable Channel 10 and Channel 11
Enable Channel 12 and Channel 13
Access
RW
RW
Table 29. Global Mode and Enable Control
Address Bits Bit Name
0x0005 [7:6] SYNC Pin Mode
Selection[1:0]
5
CLKIN1/CLKIN1 in
external VCO input
mode
4
CLKIN0/CLKIN0 in RF
SYNC input mode
[3:0] PLL1 Reference Path
Enable[3:0]
Settings
00
01
10
11
Bit 0
Bit 1
Bit 2
Bit 3
Description
SYNC pin configuration with respect to PLL2.
Disabled.
SYNC. A rising edge is carried through PLL2. Useful for multichip
synchronization.
Pulse generator. Request a pulse generator stream from any channels
configured for dynamic startup. This behaves in the same way as a GPI
requested pulse generator.
Causes SYNC if alarm exists, otherwise causes pulse generator.
CLKIN1/CLKIN1 input is used for external VCO.
CLKIN0/CLKIN0 input is used for external RF sync.
Selects and enables the reference path for PLL1.
Enable CLKIN0/CLKIN0 input path.
Enable CLKIN1/CLKIN1 input path.
Enable CLKIN2/CLKIN2 input path.
Enable CLKIN3/CLKIN3 input path.
Access
RW
Rev. B | Page 53 of 72