HMC7044 Datasheet, PDF (41/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Table 23. Supply Network of the HMC7044 by Pin for the Clock Output Network
Per Output Channel
Digital Regulator and Other Sources
Buffer
LVPECL
CML100
High Power
Low Power
LVDS
High Power
Low Power
CMOS
Channel Mux
Digital Delay
Off
Setpoint > 1
Analog Delay
Off
Minimum Setting
Maximum Setting
Divider Logic
0
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷16
÷32
÷2044
SYNC Logic³
Slip Logic³
Subtotal
Comment
Typical Current (mA)
2.5
Including term currents
Including term currents
At 307 MHz
At 100 MHz, both sections
Glitchless mode enabled
Not using divider path
43
31
24
10
25
Included²
Included²
3
Included²
9
9
Included²
27
27
31
29
32
29
30
31
32
32
4
4
Profile¹
0 12
3
4
0.5 2.5 2.5 2.5 2.5
43 43
43
10
3
3
0
9
9
0
0
31
32
2.5 48 89 13 92
1 _{Profile 0 = sleep mode; Profile 1 = fundamental mode; Profile 2 =SYSREF channel matched to fundamental mode; Profile 3 = LVDS—high power signal source from}
other channel; Profile 4 = worst case configuration for power consumption of a channel.
2 _{The base current consumption of the circuit (for example, mux) is included in the buffer typical current.}
3 _{Currents occur only temporarily during a synchronization event.}
Rev. B | Page 41 of 72