HMC7044 Datasheet, PDF (24/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
DETAILED BLOCK DIAGRAM
RFSYNCIN/
RFSYNCIN
CLKIN0/RFSYNCIN
CLKIN0/RFSYNCIN
CLKIN1/FIN
CLKIN1/FIN
IN0 PRESCALER
(1 TO 255)
FIN/
FIN
IN1 PRESCALER
(1 TO 255)
LOS
DETECT
HOLDOVER
CLKIN3
CLKIN3
CLKIN2/OSCOUT0
CLKIN2/OSCOUT0
IN3 PRESCALER
(1 TO 255)
IN2 PRESCALER
SPI
(1 TO 255)
REF
MUX
R1 DIVIDER
(1 TO 65535)
N1 DIVIDER
(1 TO 65535)
PHASE DETECTOR
CHARGE PUMP
PLL1
CPOUT1
VCO1 ~ 2500MHz
VCO2 ~ 3000MHz
CPOUT2
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
CLKOUT2
CLKOUT2
OSCOUT1
OSCOUT1
OSCIN
OSCIN
ANALOG
MUX DELAY
MUX ANALOG
DELAY
ANALOG
MUX DELAY
VCXO PRESCALER
(1 TO 255)
OSC DIVIDER
÷1, ÷2, ÷4, ÷8
2×
2×
MUX
R2 DIVIDER
(1 TO 4095)
N2 DIVIDER
(8 TO 4095)
PHASE DETECTOR
CHARGE PUMP
PLL2
PARTIALLY
INTEGRATED INTERNAL
LOOP
VCO
FILTER
×2
OSCINBUF
CLK DISTRIBUTION PATH _VCO
MUX
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
SYSREF TIMER
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
SYNC/PULSOR
GPI
CONTROL
SPI
DIVIDER ^{EXT VCO}
÷1, ÷2
FIN/FIN
FSM
SYNC
RFSYNCIN/
RFSYNCIN
FUNDAMENTAL MODE
COARSE _DIVIDER CYCLE
DIGITAL
DELAY
(1 TO 4094)
SLIP/
SYNC
FUNDAMENTAL MODE
TO LEAF DIVIDERS
CYCLE _DIVIDER
SLIP/
SYNC
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
OSCINBUF
ANALOG
DELAY MUX
CLKOUT8
CLKOUT8
SCLKOUT3
SCLKOUT3
CLKOUT4
CLKOUT4
MUX ANALOG
DELAY
ANALOG
MUX DELAY
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE _DIVIDER CYCLE
DIGITAL
DELAY
(1 TO 4094)
SLIP/
SYNC
FUNDAMENTAL MODE
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
ANALOG MUX
DELAY
ANALOG
DELAY MUX
SCLKOUT9
SCLKOUT9
CLKOUT10
CLKOUT10
SCLKOUT5
SCLKOUT5
CLKOUT6
CLKOUT6
MUX ANALOG
DELAY
ANALOG
MUX DELAY
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
COARSE _DIVIDER CYCLE
DIGITAL
DELAY
(1 TO 4094)
SLIP/
SYNC
FUNDAMENTAL MODE
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
ANALOG MUX
DELAY
ANALOG
DELAY MUX
SCLKOUT11
SCLKOUT11
CLKOUT12
CLKOUT12
SCLKOUT7
SCLKOUT7
MUX ANALOG
DELAY
COARSE
DIGITAL
DELAY
DIVIDER
(1 TO 4094)
CYCLE
SLIP/
SYNC
FUNDAMENTAL MODE
CYCLE
SLIP/
SYNC
DIVIDER
(1 TO 4094)
COARSE
DIGITAL
DELAY
FUNDAMENTAL MODE
ANALOG MUX
DELAY
SCLKOUT13
SCLKOUT13
LDOs
DEVICE
SPI
ALARM GENERATION
CONTROL
BGA LDO LDO LDO LDO LDO LDO SDATA SCLK SLEN
BYP1 BYP2 BYP3 BYP4 BYP5 BYP6 BYP7
GPIO1 GPIO2 GPIO3 GPIO4
Figure 35. Top Level Diagram
SYNC RESET
Rev. B | Page 24 of 72