HMC7044 Datasheet, PDF (16/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
Pin No.
65
66
67
68
Mnemonic
SCLKOUT13
CLKOUT12
CLKOUT12
VCC9_OUT
EP
Type¹
O
O
O
P
Description
Complementary Clock Output Channel 13. Default SYSREF profile.
True Clock Output Channel 12. Default DCLK profile.
Complementary Clock Output Channel 12. Default DCLK profile.
Power Supply for Clock Group 0 (Northwest)—Channel 0, Channel 1, Channel 12, and Channel 13.
See the Clock Grouping, Skew, and Crosstalk section.
Exposed Pad. Connect the exposed pad to a high quality RF/dc ground.
1 _{O is output, I is input, P is power, and I/O is input/output.}
Rev. B | Page 16 of 72