HMC7044 Datasheet, PDF (33/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
Basic Output Divider Channel
Each of the 14 output channels are logically identical, and support
divide ratios from 1 to 4094. The supported odd divide ratios
(1, 3, 5) have 50.0% duty cycle. The only distinction between a
SYSREF channel and a DCLK channel is in the SPI configura-
tion and the typical usage of a given channel.
For basic functionality and phase control, each output path
consists of the following:
• Divider—generates the logic signal of the appropriate
frequency and phase
• Digital phase adjust—adjusts the phase of each channel in
increments of ½ VCO cycles
• Retimer—a low noise flip flop to retime the channel,
removing any accumulated jitter
• Analog fine delay—provides a number of ~25 ps delay steps
• Selection mux—selects the fundamental, divider, or analog
delay, or an alternate path
• Multimode output buffer—low noise LVDS, CML, CMOS,
or LVPECL
The digital phase adjuster and retimer launch on either clock
phase of the VCO, depending on the digital phase adjust setpoint
(Coarse Digital Delay[4:0]).
To support divider synchronization, arbitrary phase slips, and
pulse generator modes, the following blocks are included:
• A clock gating stage pauses the clock for synchronization
or slip operations
• An output channel leaf (×14) controller manages slip,
synchronization, and pulse generators with information
from the SYSREF FSM
Each channel has an array of control signals. Some of the controls
are described in Table 15.
HMC7044
System wide broadcast signals can be triggered from the SPI or
general-purpose input (GPI) port to issue a SYNC command
(to align dividers to the system internal SYSREF timer), issue a
pulse generator stream, (temporarily exporting SYSREF signals to
receivers), or to cause the dividers to slip a number of VCO
cycles to adjust their phases.
Individual dividers can be made sensitive to these events by
adjusting their slip enable, SYNC enable, and Start-Up Mode[1:0]
configuration, as described in Table 16.
When output buffers are configured in CMOS mode and phase
alignment is required among the outputs, additional multislip
delays must be issued for Channel 0, Channel 3, Channel 5,
Channel 6, Channel 9, Channel 10, and Channel 13. The value
of the delay must be as large as half of the selected divider ratio.
Note that this requirement of having additional multislip delays
is not needed when channels are used in LVPECL, CML or
LVDS mode.
If a channel is configured to behave as a pulse generator, to
temporarily power up and power down according to GPI, SPI,
or SYNC pin pulse generator commands, it has additional
controls to define its behavior outside of the pulse generator
chain (see Table 17).
Each divider has an additional phase offset register that adjusts
its start phase, or to influence the behavior of slip events sent
via the SPI (see Table 18).
Table 19 outlines the typical configuration combinations for a
DCLK channel relative to a SYSREF synchronization channel.
Note that other combinations are possible. Synchronization of
downstream devices can be managed manually, or by using the
pulse generator functionality of the HMC7044. See the Typical
Programming Sequence section for more information about the
differences between the two methods.
Rev. B | Page 33 of 72