HMC7044 Datasheet, PDF (29/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
Resetting the Dividers
If using tristate-based holdover, the second holdover exit
method is recommended. When a reference appears available
(LOS = 0), the FSM resets the R and N dividers and allows them
to restart immediately. This approach limits the maximum phase
error coming out of holdover to two VCXO cycles (about 8 ns
for typical VCXO frequencies). There is no need to wait an
undetermined amount of time (as in the first method of
uncontrolled release) to initiate the switch.
DAC Assisted Release
If using DAC-based holdover, the DAC and CP can set VTUNE
concurrently as the devices exits holdover. With the DAC output
impedance at a relatively low setting (for example, 5 Ω), the device
resets the dividers as in the second method, and then the CP
attempts to influence VTUNE. The CP fails, with the DAC sinking
the current it is trying to inject into the VTUNE node. Gradually,
the device increases the output impedance of the DAC, and the
CP gains more influence to manipulate VTUNE, pulling the phases
into alignment. Using this DAC assisted CP release method
limits the holdover exit transients to within ~1 ppm.
Figure 39 to Figure 41 compare the holdover release methods:
resetting the dividers vs. DAC assisted release, and uncontrolled
release (which starts with a phase error of up to one PFD
period) as the device exits holdover and reacquires to a
reference signal.
20
16
12
RESET DIVS
8
4
0
–4
–8
–12
–16
–20
–10 0 10 20 30 40 50 60 70 80 90
TIME (ms)
Figure 39. Resetting the Dividers
HMC7044
20
16
12
DAC RELEASE
8
4
0
–4
–8
–12
–16
–20
–10 0 10 20 30 40 50 60 70 80 90
TIME (ms)
Figure 40. DAC Assisted Release
20
16
12
DO NOTHING
8
4
0
–4
–8
–12
–16
–20
–10 0 10 20 30 40 50 60 70 80 90
TIME (ms)
Figure 41. Wait for Zero Phase Error (No Divider Reset)
PLL1 Programming Considerations
Configuring Reference Inputs for PLL1 vs. Other Uses
To use the four reference clocks for PLL1, the input buffer must
be enabled and selected as a relevant path for PLL1.
Table 13. Input Buffer and Reference Path Settings
Bit Name
Description
Buffer Enable
Enable the input buffer (where x = 0,
1, 2, 3, or V for VCXO) via
Register 0x000A to Register 0x000E
PLL1 Reference Path
Enable[3:0]
Select one of four available reference
paths for PLL1
Because the CLKIN0/RFSYNCIN, CLKIN0/RFSYNCIN,
CLKIN1/FIN, and CLKIN1/FIN pins can be configured for
output network purposes, and the CLKIN2/OSCOUT0 and
CLKIN2/OSCOUT0 pins can function as oscillator outputs, the
SPI bits in Table 14 must be configured accordingly.
Rev. B | Page 29 of 72