HMC7044 Datasheet, PDF (68/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
Address
0x00CE, 0x00D8, 0x00E2,
0x00EC, 0x00F6, 0x0100,
0x010A, 0x0114, 0x011E,
0x0128, 0x0132, 0x013C,
0x0146, 0x0150
0x00CF, 0x00D9, 0x00E3,
0x00ED, 0x00F7, 0x0101,
0x010B, 0x0115, 0x011F,
0x0129, 0x0133, 0x013D,
0x0147, 0x0151
0x00D0, 0x00DA, 0x00E4,
0x00EE, 0x00F8, 0x0102,
0x010C, 0x0116, 0x0120,
0x012A, 0x0134, 0x013E,
0x0148, 0x0152
0x00D1, 0x00DB, 0x00E5,
0x00EF, 0x00F9, 0x0103,
0x010D, 0x0117, 0x0121,
0x012B, 0x0135, 0x013F,
0x0149, 0x0153
1 _{X means don’t care.}
Bits Bit Name
[7:4] Reserved
[3:0] 12-Bit Multislip
Digital Delay[11:8]
(MSB)
[7:2] Reserved
[1:0] Output Mux
Selection[1:0]
[7:6] Force Mute[1:0]
5 Dynamic driver
enable
[4:3] Driver Mode[1:0]
[2] Reserved
[1:0] Driver
Impedance[1:0]
[7:0] Reserved
Settings¹
Description
Reserved.
12-bit multislip digital delay amount MSB.
Reserved.
Channel output mux selection.
00
Channel divider output.
01
Analog delay output.
10
Other channel of the clock group pair.
11
Input VCO clock (fundamental). Fundamental can also
be generated with 12-Bit Channel Divider[11:0] = 1.
Idle at Logic 0 selection (pulse generator mode only).
Force to Logic 0 or VCM.
00
Normal mode (selection for DCLK).
01
Reserved.
10
Force to Logic 0.
11
Reserved.
Dynamic driver enable (pulse generator mode only).
0
Driver is enabled/disabled with channel enable bit
1
Driver is dynamically disabled with pulse generator
events.
Output driver mode selection.
00
CML mode.
01
LVPECL mode.
10
LVDS mode.
11
CMOS mode.
Reserved.
Output driver impedance selection for CML mode.
00
Internal resistor disable.
01
Internal 100 Ω resistor enable per output pin.
10
Reserved.
11
Internal 50 Ω resistor enable per output pin.
Reserved.
Access
RW
RW
RW
RW
Rev. B | Page 68 of 72