HMC7044 Datasheet, PDF (14/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
CLKOUT0 1
CLKOUT0 2
SCLKOUT1 3
SCLKOUT1 4
RESET 5
SYNC 6
BGABYP1 7
LDOBYP2 8
LDOBYP3 9
VCC1_VCO 10
LDOBYP4 11
LDOBYP5 12
SCLKOUT3 13
SCLKOUT3 14
CLKOUT2 15
CLKOUT2 16
VCC2_OUT 17
HMC7044
TOP VIEW
(Not to Scale)
51 VCC7_PLL2
50 CPOUT2
49 LDOBYP7
48 OSCIN
47 OSCIN
46 LDOBYP6
45 OSCOUT1
44 OSCOUT1
43 CLKIN2/OSCOUT0
42 CLKIN2/OSCOUT0
41 VCC6_OSCOUT
40 CLKIN0/RFSYNCIN
39 CLKIN0/RFSYNCIN
38 VCC5_PLL1
37 CLKIN1/FIN
36 CLKIN1/FIN
35 RSV
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A HIGH QUALITY RF/DC GROUND.
Figure 2. Pin Configuration
Table 12. Pin Function Descriptions
Pin No. Mnemonic
Type¹ Description
1
CLKOUT0
O
True Clock Output Channel 0. Default DCLK profile.
2
CLKOUT0
O
Complementary Clock Output Channel 0. Default DCLK profile.
3
SCLKOUT1
O
True Clock Output Channel 1. Default SYSREF profile.
4
SCLKOUT1
O
Complementary Clock Output Channel 1. Default SYSREF profile.
5
RESET
I
Device Reset Input. Active high. For normal operation, set RESET to 0.
6
SYNC
I
Synchronization Input. This pin is used for multichip synchronization. If not used, set SYNC to 0.
7
BGABYP1
Band Gap Bypass Capacitor Connection. Connect a 4.7 µF capacitor to ground. This pin affects all
internally regulated supplies.
8
LDOBYP2
LDO Bypass 2. Connect a 4.7 µF capacitor to ground. The internal digital supply is 1.8 V. This pin is
the LDO bypass for the PLL1, PLL2, and SYSREF sections.
9
LDOBYP3
LDO Bypass 3. Connect a 4.7 µF capacitor to ground. This pin is the 2.8 V supply to PLL1, Phase
Frequency Detector 1 (PFD1), Charge Pump 1 (CP1), RF synchronization (RFSYNC), and Pin 36
buffers.
10
VCC1_VCO
P
3.3 V Supply for VCO and VCO Distribution.
11
LDOBYP4
LDO Bypass 4. Connect a 1 µF capacitor to ground. This pin is the first stage regulator for the VCO
supply.
12
LDOBYP5
LDO Bypass 5. Connect a 100 nF capacitor to LDOBYP4. This pin is the VCO core supply voltage.
13
SCLKOUT3
O
True Clock Output Channel 3. Default SYSREF profile.
14
SCLKOUT3
O
Complementary Clock Output Channel 3. Default SYSREF profile.
15
CLKOUT2
O
True Clock Output Channel 2. Default DCLK profile.
16
CLKOUT2
O
Complementary Clock Output Channel 2. Default DCLK profile.
17
VCC2_OUT
P
Power Supply for Clock Group 1 (Southwest)—Channel 2 and Channel 3. See the Clock Grouping,
Skew, and Crosstalk section.
18
SLEN
I
SPI Latch Enable.
Rev. B | Page 14 of 72