HMC7044 Datasheet, PDF (28/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
PLL1 Holdover Entry Shortcut
The recommended methods are as follows:
When a reference fails, the LOS circuit takes a number of LCM
clock cycles to recognize the problem and to request the PLL1
FSM enter holdover and tristate the CP. By that time, if one of
the missing edges is needed to trigger the R divider output, the
PFD and CP have already saturated, pulling current out of the
loop filter for these cycles, and disturbing the holdover frequency.
The probability of this happening decreases as the PFD rate
decreases relative to fLCM, but it is not eliminated. The HMC7044
includes a unique feature to prevent this type of frequency
runaway.
A sensor watches the up/down pulses from the PFD (see
Figure 35). When locked, the pulse width is small, based on any
small signal error, PFD/CP offset, and the reset delay of the PFD. If
the device is in the locked state and has a phase error that is larger
than expected (~4 ns), it is a sign that the reference has failed, and
the device immediately tristates the pump, reducing the amount
of time charge can be extracted from the loop from about five
LCM cycles (162 ns at 30.72 MHz) to <4 ns. This error indication
also invalidates the lock detect. When the FSM acknowledges
the issue, it holds the CP in tristate. When using the optional
DAC-based holdover, the FSM instructs the ADC/DAC that is
tracking the VTUNE voltage to switch from sense mode to force
mode, holding it steady to within 1 LSB (about 20 mV or 0.4 ppm)
until the HMC7044 senses a stable reference and transitions out
of holdover.
• Wait for zero phase error (no divider reset): wait for LOS =
0 and low phase error at PFD (Holdover Exit Criteria[1:0] = 1,
Holdover Exit Action[1:0] = 1)
• Resetting the dividers: wait for LOS = 0 and reset the
R1/N2 dividers (Holdover Exit Criteria[1:0] = 0, Holdover
Exit Action[1:0] = 0)
• DAC assisted release: wait for LOS = 0, reset R1/N2, and
configure for DAC assisted release (Holdover Exit
Criteria[1:0] = 0, Holdover Exit Action[1:0] = 3)
Wait for Zero Phase Error
While the CP is still in tristate, the FSM monitors the PDF for a
cycle slip indication as the candidate reference and VCXO signal
cross each other. The crossing of the reference and VCXO phases
eventually occurs but can take a long time, as determined by the
inherent frequency error due to an imperfect holdover. Just after a
cycle slip event, the phase error at the PFD is at its minimum
value, and there is minimal glitch as the PLL reacquires. Figure 38
shows an example where the reference is removed and PLL1
goes into tristate-based holdover. After approximately 7 sec, the
reference is restored and, about a second later, the phases cross
and the PLL reacquires, all with less than 0.15 ppm of deviation
from the original frequency value.
1.0
0.8
PLL1 Holdover Steady State
0.6
When in the holdover state, the user has the following two
options:
0.4
TRISTATE HOLDOVER MODE ≈ 8 SECONDS
0.2
• Tristate the CP
• Tristate the CP and engage the holdover DAC
When in tristate mode, the HMC7044 has a very high
impedance charge pump output (~10 GΩ). This output is
normally an insignificant contributor to PLL1 VTUNE leakage,
which is determined primarily by the on-board loop filter
components and the VCXO tuning port. This mode allows the
tuning voltage to maintain itself for significant periods while in
holdover.
0
–0.2
ENABLE REFERENCE AND LOCK
–0.4
–0.6
–0.8
–1.0
0 1 2 3 4 5 6 7 8 9 10
TIME (Seconds)
Figure 38. Frequency Deviation from Nominal vs. Time of Tristate Holdover
Entry and Exit When the Phases Cross Zero
To accommodate indefinite periods in holdover, or to ensure
VTUNE is driven and not susceptible to drift, the second option
(set via the holdover uses DAC bit in Register 0x0029, Bit 2)
forces the VTUNE voltage to its time averaged value, obtained by
low-pass filtering the ADC value while the PLL is reporting
lock. The holdover sensing ADC and the driving DAC are seven
bits each, and have an LSB of approximately 19 mV.
This first method of uncontrolled release suffers from an
indeterminate amount of time for the phases to cross and exit
holdover. However, if it takes 1 sec for the phases to cross, the
frequencies are off by only 1 Hz. If it takes 10 sec to cross, the
error is 0.1 Hz. If the error is so low that it takes a long time to
exit holdover, the device is effectively frequency locked. In some
applications, being open-loop for this long of a duration can be
PLL1 Holdover Exit
acceptable, considering the very small frequency errors. Although
The transition out of holdover can happen in three ways and is
controlled by the Holdover Exit Criteria[1:0] bits and the Holdover
this method of holdover exit is very smooth, it can take a very
long time to occur.
Exit Action[1:0] bits in Register 0x0016 (see the Control Register
Map Bit Descriptions section for details), which describes the
steps that the FSM takes as the HMC7044 exits holdover and
acquires lock.
Rev. B | Page 28 of 72