HMC7044 Datasheet, PDF (40/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
Table 22. Supply Network of the HMC7044 by Pin for PLL1, PLL2, VCO, and SYSREF
Circuit Block
VCC5_PLL1
CLKIN1/CLKIN1
Comment
Used as a PLL1 reference
Typical Current
(mA)
2
CLKIN1/CLKIN1 Buffer
CLKIN0/CLKIN0
Extra if used as buffer for external
5
VCO
Used as a PLL1 reference
2
CLKIN0/CLKIN0 Buffer
Extra current if used as RF
5
synchronization buffer²
External VCO Path (fOUT)
18
External VCO Path
Extra current for divide by 2
10
External RF Synchronization Path³
3
Regulator to 1.8 V, Bypassed on LDOBYP2 N2, digital functions
2
PLL1 Functions
LOS, R1, N1, FSMs
10
PLL2 Functions
R2, N2, lock detect
17
SYSREF Timer
1
GPO Drivers in High Speed Mode⁴
Regulator to 2.8 V, Bypassed on LDOBYP3
2
PLL1 PFD/CP
7
PLL1 DAC Holdover Circuits
2
CLKIN2/CLKIN2 Buffer
2
CLKIN3/CLKIN3 Buffer
2
Subtotal for VCC5_PLL1
90
VCC7_PLL2
Regulator to 2.8 V, Bypassed on LDOBYP7
2
PLL2 PFD, Doubler, and R2 and N2
21
Outputs
PLL2 Charge Pump
8
Regulator to 2.8 V, Bypassed on LDOBYP6
2
VCXO Buffer
16
OSCOUTx/OSCOUTx Divider/Mux⁵
8
Subtotal for VCC7_PLL2
57
VCC1_VCO
VCO Distribution Network
Minimum possible value
71
Sync Retiming Network
Minimum possible value⁶
8
VCO Regulator, Bypass to LDOBYP4 and
84
LDOBYP5
VCO Core
Subtotal for VCC1_VCO
163
VCC3_SYSREF
SYSREF Input Network³
11
SYSREF Counter Base
12
SYSREF Counter, SYNC network
4
Subtotal for VCC3_SYSREF
27
Subtotal (Without Output Paths)
Profile¹
01 23 4 5
22
2
22
55
18
22 22 2 2
10 10
17
17 17
1
22 22 2 2
77
2
2
2
4 49 23 21 46 11
22 22 2 2
4 21
21 21
8
88
22 22 2 2
16 16 16 16
8 49 20 49 49 4
8 71 0 71 71 71
84
84
8 155 0 155 71 71
12
12
0 12 0 0 0 12
20 265 43 225 166 98
1 _{Profile 0 = sleep mode; Profile 1 = power-up defaults, PLL1 with four references and PLL2 locked with internal VCO, SYSREF timer running; Profile 2 = PLL1 only, one}
reference; Profile 3 = PLL2 + VCO, PLL1 disabled, Profile 4 = PLL2 with external VCO, PLL1 disabled, Profile 5 = fanout mode only, SYSREF running.
2 _{This is the incremental amount of current for the circuit when put in this mode. For example, the CLKIN0/CLKIN0 buffer used for PLL1 reference path is 2 mA. If it is}
used as the external synchronization buffer instead, it is 2 + 5 mA.
3 _{The transient current in PLL2 synchronization mode can be temporarily enabled when using external synchronization.}
4 _{The current is highly dependent on rate of input/output and load of input/output traces. For heavily loaded traces, it is recommended to use a series resistance of}
~100 Ω to minimize the IR drop on the internal regulator during transitions.
5 _{The function varies from 8 mA to 14 mA depending on divide ratio.}
6 _{A temporary current only.}
Rev. B | Page 40 of 72