HMC7044 Datasheet, PDF (52/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
Addr.
(Hex)
0x014A
0x014B
0x014C
0x014D
0x014E
0x014F
0x0150
0x0151
Register
Name
Channel
Output 13
control
0x0152
0x0153
Bit 7 (MSB) Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
High
performance
mode
SYNC
enable
Slip enable Reserved
Start-Up Mode[1:0]
Multislip Channel
enable
enable
12-Bit Channel Divider[7:0] (LSB)
Reserved
12-Bit Channel Divider[11:8] (MSB)
Reserved
Fine Analog Delay[4:0]
Reserved
Coarse Digital Delay[4:0]
12-Bit Multislip Digital Delay[7:0] (LSB)
Reserved
12-Bit Multislip Digital Delay[11:8] (MSB)
Reserved
Output Mux
Selection[1:0]
Force Mute[1:0]
Dynamic
driver enable
Driver Mode[1:0]
Reserved Driver Impedance[1:0]
Reserved
Default
Value
(Hex)
0xFD
0x00
0x01
0x00
0x00
0x00
0x00
0x00
0x30
0x00
CONTROL REGISTER MAP BIT DESCRIPTIONS
Global Control (Register 0x0000 to Register 0x0009)
Table 26. Global Soft Reset Control
Address Bits Bit Name Settings
0x0000 [7:1] Reserved
0 Soft reset
Description
Reserved.
Resets all registers, dividers, and FSMs to default values.
Access
RW
Table 27. Global Request and Mode Control
Address Bits Bit Name
Settings
0x0001 7
Reseed request
6
High performance
distribution path
0
1
5
High performance
PLLs/VCO
0
1
4
Force holdover
3
Mute output drivers
2
Pulse generator request
1
Restart dividers/FSMs
0
Sleep mode
Description
Requests the centralized resync timer and FSM to reseed any of the
output dividers that are programmed to pay attention to sync events.
This signal is rising edge sensitive, and is only acknowledged if the
resync FSM has completed all events (has finished any previous pulse
generator and/or sync events, and is in the done state; SYSREF FSM
State[3:0] = 0010).
High performance distribution path select. The VCO clock distribution
path has two modes.
Power priority.
Noise priority. Provides the option for better noise floors on the
divided output signals.
High performance PLL/VCO select. The VCO has two modes of
operation.
Power priority.
Noise priority. Reduces the phase noise around the carrier.
Force PLL1 into holdover mode. A holdover request from the GPI or SPI
is debounced inside the device when transferred to the PLL1 FSM
clock domain (which is nominally at the VCXO or LCM rate). With the
debouncer enabled, the delay from force holdover assertion to the
HOLDOVER state is six clock cycles. If the debouncer is bypassed, the
delay is two clock cycles. To asynchronously tristate the charge pump,
the user can disable the up and down signals from the PFD via Bits[4:3]
(PLL1 PFD up enable, PLL1 PFD down enable) in the PLL1 PFD control
register (Register 0x001B).
Mutes the output drivers (dividers still run in the background).
Asks for a pulse stream (see the Typical Programming Sequence
section).
Resets all dividers and FSMs. Does not affect configuration registers.
Forces shutdown. PLL1 and PLL2, output network, and I/O buffers are
disabled.
Access
RW
Rev. B | Page 52 of 72