HMC7044 Datasheet, PDF (31/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
VCO Selection, External VCO Use
~2.5GHz
VCO
VCO ENABLE[1:0] = 10
AUTOCAL
~3.0GHz
VCO
VCO ENABLE[1:0] = 01
CLKIN1/CLKIN1
IN EXTERNAL VCO
INPUT MODE = 1
TO PLL2
N2 DIVIDER
TO
OUTPUT
NETWORK
÷2
DIVIDE BY 2 ON
EXTERNAL VCO ENABLE
Figure 43. VCO Input Network
VCO Calibration
The on-board VCOs contain an AGC loop that regulates the
core voltage of the oscillator to achieve the desired swing and
thus the trade-off between phase-noise and power consump-
tion. This AGC loop uses large external bypass capacitors to
eliminate the noise impact of the AGC loop, and therefore takes
time to settle after power-up, sleep, or after changing the VCO
Selection[1:0] setting. With the 100 nF/1 μF configuration,
settling time takes approximately 10 ms (typical).
Each of the VCOs in the HMC7044 has 32 frequency bands.
Normally, three or more subbands can synthesize any particular
frequency, and an on-board autotune algorithm selects the solution
that provides tuning margin for temperature fluctuations. Temp-
erature compensation is applied inside to ensure the device can
be calibrated at any frequency and maintain lock as the frequency is
carried to any other frequency in the operating range.
The autotune is triggered by toggling the restart dividers/FSMs
bit in Register 0x0001, Bit 1, after R2 and N2 are programmed,
the VCXO is applied, and the VCO peak detector loop has settled.
When the VCXO is applied to the system and the R2 and N2
divide ratios are programmed, the autotune algorithm has the
information needed to find the appropriate band of the VCO.
Multichip Synchronization via PLL2
To synchronize multiple HMC7044 devices together, it is recom-
mended to use the SYNC input pin. If the SYNC pin transitions
from 0 to 1 with sufficient setup/hold margin with respect to the
VCXO, this synchronization event is deterministically carried
through PLL2, up the timing chain through the N2 divider, and
then to the master SYSREF timer (see the Clock Output Network
section for more information). This mechanism of deterministic
phase adjustment allows synchronization of the SYSREF timer
and output phases of multiple HMC7044 devices.
HMC7044
Apply the SYNC input rising edge only once. After sensing the
rising edge on the VCXO domain, the SYNC input is ignored
for the next 16 × 6 tPD2 periods as the FSM processes the event.
After this period expires, the FSM becomes sensitive again to
the SYNC pin. If the SYNC is applied periodically, the first edge
initializes the synchronization process, and then the subsequent
edges may or may not be recognized depending on their
width/repetition rate with respect to 16 × 6 tPD2.
Note that the SYNC rising edge must be provided cleanly with
respect to the HMC7044 VCXO input pin (OSCIN/OSCIN).
The user normally has access to the CLKINx/CLKINx pins of
PLL1, and not to the VCXO signal directly. When PLL1 is locked,
however, the VCXO rising edge is roughly aligned to the PLL1
active reference, and, therefore, the user has indirect knowledge
of the phase of the VCXO. The VCXO is also available as an
output of the HMC7044, if the user wants to retime the SYNC
signal more directly.
The phase offset of the PLL1 active reference with respect to the
VCXO is a function of the internal delay of each path. This base
delay offset is a function of deterministic conditions (LCM, R1,
N1 divider setpoints, termination setups, and slew rates), but is also
subject to PVT variations that compress or exaggerate this offset.
For most practical purposes, the multichip synchronization
feature is limited to PLL1 reference rates <200 MHz.
CLOCK OUTPUT NETWORK
In the HMC7044, PLL1 is responsible for frequency cleanup,
redundancy, and hitless switching. PLL2 and the VCOs handle
integrated jitter and performance at an 800 kHz offset. Although
the PLL1/PLL2 and VCXO components are important, much of
the uniqueness of a JESD204B clock generation chip relates to
its array of output channels.
In a device such as the HMC7044, some of the output network
requirements include the following:
• Very good phase noise floor of the DCLK channels that can
be connected to critical data converter sample clock inputs
• A large number of DCLK and SYSREF channels
• Deterministic phase alignment between all output channels
relative to one another
• Fine phase control of synchronization channels with
respect to the DCLK channel
• Frequency coverage to satisfy typical clock rates in
expectant systems
• Skew between SYSREF and DCLK channels that is much
less than a DCLK period
• Spur and crosstalk performance that does not impact
system budgets
Rev. B | Page 31 of 72