HMC7044 Datasheet, PDF (45/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Addr.
(Hex)
0x0017
0x0018
0x0019
0x001A
0x001B
0x001C
0x001D
0x001E
0x001F
0x0020
0x0021
0x0022
0x0026
0x0027
0x0028
0x0029
0x002A
PLL2
0x0031
0x0032
0x0033
0x0034
Register
Name
PLL1
holdover
DAC/ADC
control
PLL1 LOS
mode control
PLL1 charge
pump control
PLL1 PFD
control
CLKIN0/
CLKIN0 input
prescaler
control
CLKIN1/
CLKIN1 input
prescaler
control
CLKIN2/
CLKIN2 input
prescaler
control
CLKIN3/
CLKIN3 input
prescaler
control
OSCIN/OSCIN
Input
prescaler
control
PLL1
reference
divider
control (R1)
PLL1
feedback
divider
control (N1)
PLL1 lock
detect
control
PLL1
reference
switching
control
PLL1 holdoff
time control
PLL2
miscellaneou
s control
PLL2
frequency
doubler
control
PLL2
reference
divider
control (R2)
Bit 7 (MSB) Bit 6
Reserved
Bit 5
Reserved
Reserved
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Holdover DAC Value[6:0]
ADC
tracking
disable
Force
DAC to
holdover
in quick
mode
Holdover BW
Reduction[1:0]
Reserved
LOS
bypass
input
prescaler
LOS uses
VCXO
prescaler
PLL1 CP Current[3:0]
Reserved
PLL1 PFD up
enable
PLL1 PFD
down
enable
CLKIN0/CLKIN0 Input Prescaler[7:0]
PLL1 PFD
up force
PLL1 PFD
down
force
PLL1 PFD
polarity
CLKIN1/CLKIN1 Input Prescaler[7:0]
CLKIN2/CLKIN2 Input Prescaler[7:0]
CLKIN3/CLKIN3 Input Prescaler[7:0]
OSCIN/OSCIN Input Prescaler[7:0]
Reserved
Reserved
16-Bit R1 Divider[7:0] (LSB)
16-Bit R1 Divider[15:8] (MSB)
16-Bit N1 Divider[7:0] (LSB)
16-Bit N1 Divider[15:8] (MSB)
PLL1 lock
detect uses
slip
Bypass
debouncer
PLL1 Lock Detect Timer[4:0]
Manual Mode Reference
Switching[1:0]
Holdoff Timer[7:0]
Holdover
uses DAC
Auto-
revertive
reference
switching
Auto-
mode
reference
switching
Reserved
Reserved
Reserved
12-Bit R2 Divider[7:0] (LSB)
Bypass
frequency
doubler
12-Bit R2 Divider[11:8] (MSB)
Rev. B | Page 45 of 72
Default
Value
(Hex)
0x00
0x04
0x00
0x08
0x18
0x04
0x01
0x04
0x01
0x04
0x04
0x00
0x10
0x00
0x0F
0x05
0x00
0x01
0x01
0x02
0x00