HMC7044 Datasheet, PDF (4/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
DIGITAL INPUT/OUTPUT (I/O) ELECTRICAL SPECIFICATIONS
Table 3.
Parameter
DIGITAL INPUT SIGNALS (RESET, SYNC, SLEN, SCLK)
Safe Input Voltage Range¹
Input Load
Input Voltage
Input Logic High (VIH)
Input Logic Low (VIL)
SPI Bus Frequency
DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS
INPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)
Safe Input Voltage Range¹
Input Capacitance
Input Resistance
Input Voltage
Input Logic High (VIH)
Input Logic Low (VIL)
Input Hysteresis
GPIO1 TO GPIO4 ALARM MUXING/DELAY
Delay from Internal Alarm/Signal to General-Purpose
Output (GPO) Driver
DIGITAL BIDIRECTIONAL SIGNALS CONFIGURED AS
OUTPUTS (SDATA, GPIO4, GPIO3, GPIO2, GPIO1)
CMOS MODE
Logic 1 Level
Logic 0 Level
Output Drive Resistance (RDRIVE)
Output Driver Delay (tDGPO)
Maximum Supported DC Current¹
OPEN-DRAIN MODE¹
Logic 1 Level
Logic 0 Level
Pull-Down Impedance
Maximum Supported Sink Current
Min Typ
−0.1
0.3
1.2
0
−0.1
0.4
50G
1.22
0
0.2
2
Max Unit Test Conditions/Comments
+3.6 V
pF
VCC V
0.5 V
10 MHz
+3.6 V
pF
Ω
VCC V
0.24 V
V
Occurs around 0.85 V
ns Does not include tDGPO
1.6 1.9
2.2 V
0
0.1 V
50
Ω
1.5 + 42 ×
CLOAD
ns Approximately 1.5 ns + 0.69 × RDRIVE × CLOAD
(CLOAD in nF)
0.6 mA
External 1 kΩ pull-up resistor
3.6 V
3.6 V maximum permitted; specifications
set by external supply
0.13
0.28 V
Against a 1 kΩ external pull-up resistor to
3.3 V
60
Ω
5
mA
1 _{Guaranteed by design and characterization.}
Rev. B | Page 4 of 72