HMC7044 Datasheet, PDF (11/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
Parameter
OUTPUT NETWORK FLOOR FOM
CML with 100 Ω Internal Termination (CML100)
Fundamental Mode
Divide by 1 to Divide by N
Divide by 1 to Divide by N
LVPECL
Fundamental Mode
Divide by 1 to Divide by N
LVDS
Divide by 1 to Divide by N
Divide by 1 to Divide by N
PHASE NOISE DEGREDATION DUE TO HARMONICS³
Fundamental Only
Third Harmonic
Third and Fifth Harmonics
Third, Fifth, and Seventh Harmonics
Third, Fifth, Seventh, and Ninth Harmonics
Third Through 61^st Harmonics
PHASE NOISE FLOOR AND JITTER
Phase Noise Floor at fOUT
Jitter Density of Floor at fOUT
RMS Additive Jitter Due to Floor
Min Typ
Max Unit
Test Conditions/Comments
−157.1
dBc/Hz Offset = 100 MHz
102
fs
Integrated jitter 12 kHz to 20 MHz
−250
−248
−247
dBc/Hz
dBc/Hz
dBc/Hz
High performance
High performance
Low power (4 dB less power)
−250
−247
dBc/Hz
dBc/Hz
−244
−243
dBc/Hz High performance
dBc/Hz Low power (4 dB less power)
0.00
dB
0.25
dB
0.40
dB
0.50
dB
0.53
dB
0.64
dB
Determined by formula⁴
Determined by formula⁵
Determined by formula⁶
dBc/Hz
sec/√Hz
sec
From fOUT and output channel FOM
1 _{PLL2 locked at 122.88 MHz × 2 × 10, wide (600 kHz) loop filter for best 12 kHz to 20 MHz jitter, CML100 high performance output buffer.}
2 _{PLL2 locked at 122.88 MHz × 2 × 12, narrow loop for best 800 Hz offset, CML100 high performance output buffer.}
3 _{When the harmonics of the signal are captured in the measurement bandwidth of the receiving instrument/circuit, the noise power of those harmonics can fold and}
influence the overall noise. Their presence causes a decibel for decibel influence. For example, if the third harmonic is at −10 dBc, there is an additional noise
contributor of 10 dB lower than the fundamental at all offsets that folds in-band and causes a 0.2 dB hit overall. The influence of the harmonics factoring into the
degradation is primarily a function of the frequency of the buffer bandwidth relative to the third, fifth, and seventh harmonics. As the output frequency reduces, more
harmonics fall into the observation bandwidth, and the degradation worsens, but only slightly. This effect produces a penalty of 0.65 dB maximum if harmonics up to
the 61^st harmonic is included.
4 _{See the Phase Noise Floor and Jitter section for more information on how to calculate the phase noise floor.}
5 _{See the Phase Noise Floor and Jitter section for more information on how to calculate the jitter density of floor.}
6 _{See the Phase Noise Floor and Jitter section for more information on how to calculate the rms additive jitter due to floor.}
CLOCK OUTPUT DRIVER CHARACTERISTICS
Table 10.
Parameter
CML MODE (LOW POWER)
−3 dB Bandwidth
Output Rise Time
Output Fall Time
Output Duty Cycle¹
Differential Output Voltage Magnitude
Common-Mode Output Voltage
CML MODE (HIGH POWER)
3 dB Bandwidth
Output Rise Time
Output Fall Time
Min Typ
Max Unit
Test Conditions/Comments
RL = 100 Ω, 9.6 mA
1950
MHz
Differential output voltage = 980 mV p-p diff
175
ps
fCLKOUT = 245.76 MHz, 20% to 80%
145
ps
fCLKOUT = 983.04 MHz, 20% to 80%
185
ps
fCLKOUT = 245.76 MHz, 20% to 80%
145
ps
fCLKOUT = 983.04 MHz, 20% to 80%
47.5 50
52.5 %
fCLKOUT = 1075 MHz (2150 MHz/2)
1390
mV p-p diff fCLKOUT = 245.76 MHz (2949.12 MHz/12)
1360
mV p-p diff fCLKOUT = 983.04 MHz (2949.12 MHz/3)
VCC − 1.05
V
fCLKOUT = 245.76 MHz (2949.12 MHz/12)
RL = 100 Ω, 14.5 mA
1400
MHz
Differential output voltage = 1410 mV p-p diff
250
ps
fCLKOUT = 245.76 MHz, 20% to 80%
165
ps
fCLKOUT = 983.04 MHz, 20% to 80%
255
ps
fCLKOUT = 245.76 MHz, 20% to 80%
170
ps
fCLKOUT = 983.04 MHz, 20% to 80%
Rev. B | Page 11 of 72