HMC7044 Datasheet, PDF (26/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
61.44MHz
122.88MHz
38.4MHz
LOCKDET
CYCLESLIP
LOS
PLL1
FSM
FORCE V_TUNE
MAINTAIN_HOLDOVER
RESET
ADC/DAC
CONTROL
DAC
COMPARATOR
FORCE
V_TUNE
61.44MHz
RST ÷R1
9.76MHz
UP TO FSMI LOCKDET
LCM
DIVIDERS
SET
0
DQ
PFD1
PHASE
ERROR
TRISTATE _CP1
>~4ns?
RST
LOCKDET
MAINTAIN
DOWN
HOLDOVER
÷N1
LOOP
FILTER
CYCLE SLIP
DETECTED
(TO PLL1 FSM)
VCXO
TO PLL2
Figure 36. PLL1 Architecture with a Typical Frequency Configuration
122.88MHz
Lock Detect
The lock detect circuit in both PLL1 and PLL2 function the
same way. They count the number of consecutive clock cycles in
which the phase error at the PFD is below a threshold. Any phase
error above this threshold resets the counter, and the count is
restarted. When the count reaches its programmed limit, the
lock detect signal is issued and the clock of the counter is gated
off to reduce power/coupling until a large phase error restarts
the process.
Although the PLL2 loop BW is relatively well defined, the PLL1
loop BW can vary widely in any given application. The SPI word,
PLL1 Lock Detect Timer[4:0] in Register 0x0028, configures the
PLL1 lock detect timer and looks for 2^{PLL1 Lock Detect Timer[4:0]}
consecutive LCM clock cycles with a phase-error <~4 ns to
issue the lock detect. Because the loop BW of PLL1 can vary
drastically depending on the application, the user must set up
the threshold such that 2^{PLL1 Lock Detect Timer[4:0]} LCM periods is on
the order of 2× to 4× the loop time constant. For example, for
fLCM = 61.44 MHz, and a loop BW of 200 Hz, set PLL1 Lock Detect
Timer[4:0] = 19 or 20. If the value is set much higher, the lock
detect circuit takes an unnecessary length of time to indicate
lock after the phases stabilize. If the value is set much lower (for
example, much less than a loop time constant), it can improperly
indicate lock during acquisition, which can cause the PLL1
finite state machine (FSM) to improperly fall in and out of
holdover mode.
Holdover/Reference Switching Overview
When switching between redundant references, or when all
references are gone and the PLL1 is left open loop, there are
often requirements to prevent frequency deviations that can
cause downstream circuits and traffic links to overrun FIFOs
and/or lose lock themselves.
PLL1 can operate in manual or automode (via the automode
reference switching bit). In manual mode, the user selects the
active reference using Manual Mode Reference Switching[1:0]
in Register 0x0029 and determines whether to go into holdover
(via the force holdover bit). In automode, the PLL1 FSM uses
the loss of signal (LOS) information, phase error data, lock
detect, and configuration data from the SPI to determine how
to handle reference interruptions. In either mode, all status
indicators are available, but PLL1 only takes evasive action in
automode. Figure 37 shows a simplified state diagram of the
PLL1 FSM.
During reset, PLL1 is held in the initialization (INIT) state. When
reset is deasserted, during the preload state, the enabled reference
paths, the reference priority table, and LOS indicators are examined
to select the best reference, and, on the next cycle, it attempts to
lock. After the requisite number of counts has elapsed with low
phase error, lock detect is asserted and PLL1 transitions to the
locked state. When PLL1 is locked, a loss of lock, LOS on the active
reference, or a reference switch event initiated by a priority clash
transitions the FSM to enter holdover, where it tristates the CP and
potentially forces VTUNE with the holdover DAC. When a stable
clock is available and other optional conditions are met, the FSM
exits holdover. Exiting holdover is handled in one of a few different
ways, designed to minimize phase/frequency hits during the
transition. Figure 37 shows a simplification of the PLL1 FSM. In
the actual implementation, the holdover state is broken into a
number of subsections corresponding to holdover entry, stable
holdover conditions, and holdover exit. The state of the PLL1
FSM is always available for a read via the SPI (PLL1 FSM State[2:0]
bits in Register 0x0082).
Rev. B | Page 26 of 72