HMC7044 Datasheet, PDF (66/72 Pages) Analog Devices – JESD204B clock generation

HMC7044
Data Sheet
Other Controls (Register 0x0096 to Register 0x00B8)
For optimum performance of the chip, Register 0x0096 to Register 0x00B8 must be programmed to a different value than their default
value.
Table 74. Reserved Registers
Address Bits Bit Name
0x0096 [7:0] Reserved
0x0097 [7:0] Reserved
0x0098 [7:0] Reserved
0x0099 [7:0] Reserved
0x009A [7:0] Reserved
0x009B [7:0] Reserved
0x009B [7:0] Reserved
0x009C [7:0] Reserved
0x009D [7:0] Reserved
0x009E [7:0] Reserved
0x009F [7:0] Reserved
0x00A0 [7:0] Reserved
0x00A1 [7:0] Reserved
0x00A2 [7:0] Reserved
0x00A3 [7:0] Reserved
0x00A4 [7:0] Reserved
0x00A5 [7:0] Reserved
0x00A6 [7:0] Reserved
0x00A7 [7:0] Reserved
0x00A8 [7:0] Reserved
0x00A9 [7:0] Reserved
0x00AB [7:0] Reserved
0x00AC [7:0] Reserved
0x00AD [7:0] Reserved
0x00AE [7:0] Reserved
0x00AF [7:0] Reserved
0x00B0 [7:0] Reserved
0x00B1 [7:0] Reserved
0x00B2 [7:0] Reserved
0x00B3 [7:0] Reserved
0x00B4 [7:0] Reserved
0x00B5 [7:0] Reserved
0x00B6 [7:0] Reserved
0x00B7 [7:0] Reserved
0x00B8 [7:0] Reserved
Settings
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Clock output driver low power setting (set to 0x4D instead of default value)
Clock output driver high power setting (set to 0xDF instead of default value)
Reserved
Reserved
Reserved
Reserved
PLL1 more delay (PFD1, lock detect) (set to 0x06 instead of default value)
Reserved
Reserved
PLL1 holdover DAC gm setting (set to 0x06 instead of default value)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VTUNE preset setting (set to 0x04 instead of default value)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Rev. B | Page 66 of 72