HMC7044 Datasheet, PDF (1/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
High Performance, 3.2 GHz, 14-Output
Jitter Attenuator with JESD204B
HMC7044
FEATURES
Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at
2457.6 MHz
Noise floor: −156 dBc/Hz at 2457.6 MHz
Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
from PLL2
Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx
frequency up to 3200 MHz
JESD204B-compatible system reference (SYSREF) pulses
25 ps analog, and ½ VCO cycle digital delay independently
programmable on each of 14 clock output channels
SPI-programmable phase noise vs. power consumption
SYSREF valid interrupt to simplify JESD204B synchronization
Narrow-band, dual core VCOs
Up to 2 buffered voltage controlled oscillator (VCXO) outputs
Up to 4 input clocks in LVDS, LVPECL, CMOS, and CML modes
Frequency holdover mode to maintain output frequency
Loss of signal (LOS) detection and hitless reference switching
4× GPIOs alarms/status indicators to determine the health of
the system
External VCO input to support up to 6000 MHz
On-board regulators for excellent PSRR
68-lead, 10 mm × 10 mm LFCSP package
APPLICATIONS
JESD204B clock generation
Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
Data converter clocking
Microwave baseband cards
Phase array reference distribution
GENERAL DESCRIPTION
The HMC7044 is a high performance, dual-loop, integer-N
jitter attenuator capable of performing reference selection and
generation of ultralow phase noise frequencies for high speed data
converters with either parallel or serial (JESD204B type) interfaces.
The HMC7044 features two integer mode PLLs and overlapping
on-chip VCOs that are SPI-selectable with wide tuning ranges
around 2.5 GHz and 3 GHz, respectively. The device is designed
to meet the requirements of GSM and LTE base station designs,
and offers a wide range of clock management and distribution
features to simplify baseband and radio card clock tree designs.
The HMC7044 provides 14 low noise and configurable outputs
to offer flexibility in interfacing with many different compo-
nents including data converters, field-programmable gate arrays
(FPGAs), and mixer local oscillators (LOs).
The DCLK and SYSREF clock outputs of the HMC7044 can be
configured to support signaling standards, such as CML, LVDS,
LVPECL, and LVCMOS, and different bias settings to offset
varying board insertion losses.
FUNCTIONAL BLOCK DIAGRAM
CLKIN0/RFSYNCIN
CLKIN0/RFSYNCIN
CLKIN1/FIN
CLKIN1/FIN
CLKIN2/OSCOUT0
CLKIN2/OSCOUT0
CLKIN3
CLKIN3
SYNC
SDATA
OSCIN
CPOUT1 OSCIN
CPOUT2 OSCOUT1 OSCOUT1
÷
PLL1
PLL2
CLKOUT0
CLKOUT0
SCLKOUT1
SCLKOUT1
CLKOUT2
CLKOUT2
SCLKOUT3
SCLKOUT3
SPI
CONTROL
INTERFACE
SYSREF
CONTROL
÷
14-CLOCK
DISTRIBUTION
CLKOUT12
CLKOUT12
SCLKOUT13
SCLKOUT13
SLEN SCLK
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com