HMC7044 Datasheet, PDF (17/72 Pages) Analog Devices – JESD204B clock generation

Data Sheet
HMC7044
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, PFD PLL1 = 7.68 MHz, PFD PLL2 = 122.88 MHz × 2; ICP1 = 1.92 mA, ICP2 = 2.56 mA (wide loop), ICP2 = 1.12 mA
(narrow loop), PLL1 loop BW ~ 70 Hz, PLL2 wide loop BW ≈ 650 kHz, PLL2 narrow loop BW ≈ 215 kHz, PLL2 narrow loop filter =
1.1 nF | 160 Ω × 33 nF; PLL2 wide loop filter = 150 pF | 430 Ω × 4.7 nF; PLL1 loop filter = 4.7 nF | 10 µF × 1.2 kΩ.
–40
–50
–60
–70
–80
–90
–100
1: 1kHz, –107.8dBc/Hz
2: 10kHz, –119.5dBc/Hz
3: 100kHz, –124.7dBc/Hz
4: 1MHz, –131.5Bc/Hz
5: 10MHz, –153.1dBc/Hz
6: 20MHz, –154.4dBc/Hz
7: 20MHz, –154.4dBc/Hz
x: START 12kHz
STOP 20MHz
CENTER 10MHz
SPAN 20MHz
1
–110
–120
–130
PLL1
CASCADED PLL1 + PLL2
2
3
4
–140 _NOISE:
–150
ANALYSIS RANGE X: BAND MARKER
ANALYSIS RANGE Y: BAND MARKER
6
–160
INTG NOISE: –66dBc/20MHz
RMS NOISE: 696µrad
57
–170
0.004°
RMS JITTER: 45fs
RESIDUAL FM: 1.6kHz
–180
1
10
100
1k
10k 100k 1M 10M
FREQUENCY (Hz)
Figure 3. Cascaded Phase Noise at 2457.6 MHz, PLL2 Wide Loop Bandwidth
–60
–70
–80
–90
–100
TOTAL PLL1 NOISE (SIMULATED)
PFD/CP NOISE (SIMULATED)
WENZEL REF (SIMULATED)
VCXO (SIMULATED)
TOTAL PLL1 NOISE (MEASURED)
–110
–120
–130
–140
–150
–160
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 6. Closed-Loop Phase Noise at 122.88 MHz, PLL1 Measurement vs.
Simulated, Clean Reference Source, ~70 Hz Loop Bandwidth 80° Phase Margin
–70
–80
–90
–100 1
2
–110
1: 1kHz, –105.3dBc/Hz
2: 10kHz, –108.5dBc/Hz
3: 100kHz, –111.4dBc/Hz
4: 800kHz, –134.2dBc/Hz
5: 1MHz, –136.5dBc/Hz
6: 10MHz, –153.3dBc/Hz
7: 20MHz, –154.6dBc/Hz
x: START 12kHz
STOP 20MHz
CENTER 10MHz
SPAN 20MHz
3
–120
–130
WIDE LOOP
NARROW LOOP
–140
NOISE:
4
5
ANALYSIS RANGE X: BAND MARKER
–150 ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –56.9dBc/20MHz
RMS NOISE: 2.0µrad
–160
.116°
RMS JITTER: 131fs
RESIDUAL FM: 1.5kHz
–170
1k
10k
100k
1M
FREQUENCY (Hz)
6
7
10M
Figure 4. Phase Noise at 2457.6 MHz, Narrow vs. PLL2 Wide Loop
Bandwidth
–60
TOTAL PLL1 OUTPUT (SIMULATED)
PFD/CP NOISE (SIMULATED)
–70
NOISY SOURCE (SIMULATED)
VCXO (SIMULATED)
–80
NOISY SOURCE, OPEN LOOP (MEASURED)
TOTAL PLL1 NOISE (MEASURED)
–90
–100
–110
–120
–130
–140
–150
–160
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 7. Closed-Loop Phase Noise at 122.88 MHz, PLL1 Measurement vs.
Simulated, Noisy Reference Source, ~70 Hz Loop Bandwidth, 80° Phase Margin
–70
–80
–90
–100
–110
–120
1
2
–130
CRYSTEK VCXO
WENZEL VCXO
1: 1kHz, –110.4dBc/Hz
2: 10kHz, –120.0dBc/Hz
3: 100kHz, –124.9dBc/Hz
4: 1MHz, –131.2dBc/Hz
5: 10MHz, –153.2dBc/Hz
6: 20MHz, –154.5dBc/Hz
7: 20MHz, –154.5dBc/Hz
x: START 12kHz
STOP 20MHz
CENTER 10MHz
SPAN 20MHz
3
4
–140
NOISE:
ANALYSIS RANGE X: BAND MARKER
–150 ANALYSIS RANGE Y: BAND MARKER
INTG NOISE: –66.1dBc/20.0MHz
RMS NOISE: 702µrad
–160
.040°
RMS JITTER: 45fs
RESIDUAL FM: 1.6kHz
–170
100
1k
10k
100k
1M
FREQUENCY (Hz)
6
57
10M
Figure 5. PLL2 Phase Noise vs. Frequency, VCXO Quality at 2457.6 MHz,
Wide Loop Bandwidth
–120
–125
–130
–135
–140
–145
–150
–155
20×LOG (800kHz WIDE LOOP)
20×LOG (800kHz NARROW LOOP)
800kHz WIDE LOOP
800kHz NARROW LOOP
–160
–165
–170
100
600 1100 1600 2100 2600 3100 3600
FREQUENCY (MHz)
Figure 8. Phase Noise vs. Frequency at Common Output Frequencies
Rev. B | Page 17 of 72