TLK6002 Datasheet, PDF (92/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
www.ti.com
Table 8-3. Device Static Latency Variance
TRANSMIT STATIC LATENCY VARIANCE – Maximum
8b/10b Encoder
Interface Mode
Serial Bit Times
Enabled
SDR
33
Enabled
DDR
33
Disabled
SDR
33
Disabled
DDR
33
Note: TX_FIFO_DEPTH[2:0] = 3'b000
Receive FIFO
Bypassed
Bypassed
Bypassed
Enabled
RECEIVE STATIC LATENCY VARIANCE – Maximum
Channel
Synchronization
8b/10b Decoder
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Serial Bit Times
30
30
20
60
Table 8-4 shows the device dynamic latency variance. Note that the dynamic latency variation is the
difference in latency when voltage and temperature are varied for a particular absolute static latency, after
traffic (including channel synchronization) has been established. The dynamic latency variance numbers
do not include phase movement between the parallel input clocks and input reference clocks.
Table 8-4. Device Dynamic Latency Variance
Transmit Dynamic Latency Variance
Minimum
Maximum
0 ns
2 ns
Receive Dynamic Latency Variance
Minimum
Maximum
0 ns
2 ns
92
Appendix D – Device Latency Specification
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