TLK6002 Datasheet, PDF (49/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
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BIT(s)
3.7
Address: 0x03
NAME
COMMA_ENABLE
3.6 DDR_ENABLE
3.5 TX_SYMBOL_ORDER
3.4 RX_SYMBOL_ORDER
3.3 ENCODE_ENABLE
3.2 DECODE_ENABLE
3.1 TX_EDGE_MODE
3.0 RX_EDGE_MODE
SLLSE34 – MAY 2010
Table 3-8. CHANNEL_CONTROL_3 (continued)
Default: 0x0180
DESCRIPTION
0 = Disables comma detection
1 = Enables comma detection (Default 1’b1)
Comma detection automatically enabled during CRPAT verification.
0 = Enables SDR data mode on parallel Transmit and Receive directions (data is
clocked only on rising edge or only on falling edge) (Default 1’b0)
1 = Enables DDR data mode on parallel Transmit and Receive directions (data
clocked on both rising and falling edge)
0 = TDx_[19:10] symbol is serialized before TDx_[9:0]. (Default 1’b0)
1 = TDx_[9:0] symbol is serialized before TDx_[19:10].
0 = RDx_[19:10] symbol is deserialized before RDx_[9:0] symbol. (Default 1’b0)
1 = RDx_[9:0] symbol is deserialized before RDx_[19:10].
Encoder enable control. Logically OR’ed with CODE*_EN pin.
0 = 8B/10B encode function is disabled (Default 1’b0)
1 = 8B/10B encode function is enabled
Encoder automatically enabled during CRPAT test pattern generation.
Decoder enable control. Logically OR’ed with CODE*_EN pin.
0 = 8B/10B decode function is disabled (Default 1’b0)
1 = 8B/10B decode function is enabled
Decoder automatically enabled during CRPAT verification.
Transmit parallel input interface mode select. (Default 1’b0)
When channel is in DDR mode
0 = Source centered timing on transmit parallel interface. Data is sampled on both
rising and falling clock edges.
1 = Source aligned timing on transmit parallel interface. Data is aligned with both
rising and falling clock edges, and a sampling point is created internal to
TLK6002 .
When channel is in SDR mode
0 = Falling edge align mode. Incoming data is aligned to falling edge of parallel
input clock. Internally data is sampled at the rising edge of the clock
1 = Rising edge align mode. Incoming parallel data is aligned to rising edge of
parallel input clock. Internally data is sampled at the falling edge of the clock.
Receive Parallel output interface mode select. (Default 1’b0)
When channel is in DDR mode:
0 = Source centered timing on receive parallel interface. Data changing is offset
from the rising and falling clock edge per the HSTL Timing specification section,
and is easily sampled by external devices.
1 = Source aligned timing on receive parallel interface. Data changes at clock edge,
and a sampling point must be created by external devices.
When channel is in SDR mode:
0 = Falling edge align mode. Outgoing parallel data is aligned to the falling edge of
the parallel output clock, and is sampled on the rising edge by external devices.
1 = Rising edge align mode. Outgoing parallel data is aligned to the rising edge of
the parallel output clock, and is sampled on the falling edge by external devices.
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
Copyright © 2010, Texas Instruments Incorporated
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