TLK6002 Datasheet, PDF (10/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
www.ti.com
Terminal
Signal
BGA
J17
H17
J16
H18
K15
K16
L14
L16
M14
TDB_[19:0]
M16
M15
P17
N14
N16
J18
M17
R17
P15
P14
P18
D18
E17
B18
C17
F16
F17
A17
B16
C16
RDB_[19:0]
D16
C18
F15
A16
B15
D15
E15
G16
H15
G15
G14
RXCLK_B
F18
PRBSB_PASS V18
CODEB_EN
V16
Table 2-1. Pin Description – Signal Pins (continued)
Direction
Type
Supply
Description
Parallel Input Channel B Transmit Data Bus.
These data signals are synchronous to and sampled by TXCLK_B.
Two data modes are supported, SDR (Single Data Rate), and DDR (Double Data Rate). SDR has two valid symbols
per TXCLK_B cycle, and DDR has four valid symbols per TXCLK_B cycle.
When input data is in 8b/10b encoded format (a.k.a. 20-bit data mode), TDB_[19:10] and TDB_[9:0] each carry a
symbol.
Input HSTL
1.5V/1.8V
VDDQB
When input data is encoded internal to TLK6002 (8b/10b encoder enabled, a.k.a. 16-bit data mode), two symbols
are input at a time, defined as follows:
One Symbol – TDB_[8] contains the control bit (k-character indication) of data byte TDB_[7:0], and TDB_[9] is
unused and should be grounded.
Other Symbol – TDB_[18] contains the control bit (k-character indication) of data byte TDB_[17:10], and TDB_[19] is
unused and should be grounded.
Unused parallel input pins must be grounded.
See the following figures for more detail:
Figure 2-1 20-bit SDR Parallel Interface Mode
Figure 2-2 16-bit SDR Parallel Interface Mode
Figure 2-3 20-bit DDR Parallel Interface Mode
Parallel Channel B Receive Data Bus.These output receive data signals are synchronous to RXCLK_B.
Two data modes are supported, SDR (Single Data Rate), and DDR (Double Data Rate). SDR has two valid symbols
per RXCLK_B cycle, and DDR has four valid symbols per RXCLK_B cycle.
When output data is in 8b/10b encoded format (a.k.a. 20-bit data mode), RDB_[19:10] and RDB_[9:0] each carry a
symbol.
When output data is decoded internal to TLK6002 (8b/10b decoder enabled, a.k.a. 16-bit data mode), two symbols
are output at a time, defined as follows:
Output
HSTL
1.5V/1.8V
VDDQB
One Symbol - RDB_[8] contains the control bit (k-character indication) of data byte RDB_[7:0], and RDB_[9]
indicates whether a 8b/10b disparity error was detected or an invalid code was received coincident with that
particular symbol
Other Symbol - RDB_[18] contains the control bit (k-character indication) of data byte RDB_[17:10], and RDB_[19]
indicates whether a 8b/10b disparity error was detected or an invalid code was received coincident with that
particular symbol.
During device reset (RESET_N asserted low) these pins are driven low. During pin based power down
(PD_TRXB_N asserted low), these pins are floating. During register based power down (1.15 asserted high), these
pins are floating.
See the following figures for more detail:
Figure 2-1 20-bit SDR Parallel Interface Mode
Figure 2-2 16-bit SDR Parallel Interface Mode
Figure 2-3 20-bit DDR Parallel Interface Mode
Output
HSTL
1.5V/1.8V
VDDQB
Receive Output Channel B Clock. RXCLK_B is synchronous to RDB_[19:0], and may be used externally to
sample Channel B output parallel data.
In SDR mode, this signal is equal in frequency to serial bit rate / 20.
In DDR mode, this signal is equal in frequency to serial bit rate / 40.
During device reset (RESET_N asserted low) this pin is driven low.
During pin based power down (PD_TRXB_N asserted low), this pin is floating.
During register based power down (1.15 asserted high), these pins are floating.
Output
LVCMOS
1.5V/1.8V
VDDO2 40Ω
Driver
Receive PRBS Channel B Error Free (Pass) Indicator
When PRBS test is enabled (PRBS_EN=1):
PRBSB_PASS=1 indicates that PRBS pattern reception is error free.
PRBSB_PASS=0 indicates that a PRBS error is detected.
During device reset (RESET_N asserted low) this pin is driven low.
During pin based power down (PD_TRXB_N asserted low), this pin is floating.
During register based power down (1.15 asserted high), this pin is floating.
It is highly recommended that PRBSB_PASS be brought to easily accessible point on the application board
(header), in the event that debug is required.
Input
LVCMOS
1.5V/1.8V
VDDO2
Encoder/Decoder Channel B Enable: When this pin is asserted high, the internal 8b/10b encoder/decoder is
enabled. This signal is OR’d with MDIO register bits, and should be tied low if software control is desired.
10
Description
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