TLK6002 Datasheet, PDF (55/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
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BIT(s)
11.15:14
Address: 0x0B
NAME
ARS_REF_FREQ[1:0]
11.13:6 ARS_SBR_ENABLE[7:0]
11.5
11.4:0
RESERVED
ARS_INTERVAL[20:16]
SLLSE34 – MAY 2010
Table 3-16. ARS_CONTROL_2
Default: 0x7FFF
DESCRIPTION
Input reference clock frequency selection in ARS mode.
00 = If input reference clock frequency is 122.88 MHz.
01 = If input reference clock frequency is 153.60 MHz. (Default 2’b01)
10 = Reserved
11 = If input reference clock frequency is 307.20 MHz.
Control to enable rate determination through ARS for each of the 8 supported bit
rates. ARS_SBR_ENABLE[7] for the highest serial bit rate and
ARS_SBR_ENABLE[0] for the lowest serial bit rate. Refer Table 2-6 for supported
serial bit rates.
For TI use only.
5 MSB’s of 21 bit wide counter defined in terms of number of REFCLK cycles to
determine amount of time that ARS state machine needs to stay in a particular
setting to achieve rate determination.
Wait time is calculated as ARS_INTERVAL[20:0] × 1024 REFCLK periods.
If ARS state machine does not achieve rate determination within the wait time
specified by this counter, ARS state machine will move into next lower serial rate
setting to achieve rate determination.
ACCESS
RW
RW
RW
RW
BIT(s)
12.15:0
Address: 0x0C
NAME
ARS_INTERVAL[15:0]
Table 3-17. ARS_CONTROL_3
Default: 0xFFFF
DESCRIPTION
16 LSB’s of 21 bit wide counter defined in terms of number of REFCLK cycles to
determine amount of time that ARS state machine needs to stay in a particular
setting to achieve rate determination.
Wait time is calculated as ARS_INTERVAL[20:0] × 1024 REFCLK periods.
If ARS state machine does not achieve rate determination within the wait time
specified by this counter, ARS state machine will move into next lowest serial rate
setting to achieve rate determination.
ACCESS
RW
BIT(s)
13.15
13.14
13.13
13.12
13.11:0
Address: 0x0D
NAME
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Table 3-18. ARS_CONTROL_4
Default: 0x3000
For TI use only.
For TI use only.
For TI use only.
For TI use only.
For TI use only.
DESCRIPTION
ACCESS
RW
BIT(s)
14.15:0
Address: 0x0E
NAME
ERROR_COUNTER[15:0]
Table 3-19. ERROR_COUNTER
Default: 0xFFFD
DESCRIPTION
In functional mode if 8b/10b decoder is enabled, this counter reflects number of
invalid code words (includes disparity errors) received by decoder.
In test pattern verification mode (7.12 = 1’b1), this counter reflects error count for the
test pattern selected through 7.10:8
When PRBS_EN pin is set, this counter reflects error count for selected PRBS
pattern. Counter value cleared to 16’h0000 when read.
ACCESS
COR
Copyright © 2010, Texas Instruments Incorporated
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