TLK6002 Datasheet, PDF (48/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
Table 3-7. AC Mode Output Swing Control
VALUE
2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
AC MODETYPICAL AMPLITUDE
(mVdfpp)
126
215
303
395
478
572
662
756
839
932
1020
1110
1190
1280
1360
1450
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Table 3-8. CHANNEL_CONTROL_3
Address: 0x03
BIT(s)
NAME
3.12:11 CH_SYNC_HYSTERESIS
[1:0]
3.10 TX_SWAP_SEL
3.9 RX_SWAP_SEL
3.8 RXCLK_OUT_SEL
Default: 0x0180
DESCRIPTION
Valid only when comma detection (channel synchronization) is enabled.
00 = The channel synchronization, when in the synchronization state, performs the
Ethernet standard specified hysteresis to return to the unsynchronized state
(Default 2’b00)
01 = A single 8b/10b invalid decode error or disparity error causes the channel
synchronization state machine to immediately transition from sync to unsync
10 = Two adjacent 8b/10b invalid decode errors or disparity errors cause the channel
synchronization state machine to immediately transition from sync to unsync
11 = Three adjacent 8b/10b invalid decode errors or disparity errors cause the
channel synchronization state machine to immediately transition from sync to
unsync
0 = Selects same channel Tx parallel interface input data as core input data for that
channel (Default 1’b0)
1 = Selects partner channel Tx parallel interface input data as core input data for
that channel
See Figure 1-4
0 = Selects same channel deserialized input data to be sent out the Rx parallel
output interface (Default 1’b0)
1 = Selects partner channel deserialized input data to be sent out the Rx parallel
output interface
See Figure 1-5
Parallel output clock (RXCLK_x) selection
When RX_SWAP_SEL (3.9) is 1’b0
0 = Selects respective channel SERDES TXBCLK clock
1 = Selects respective channel SERDES RXBCLK clock (Default 1’b1)
When RX_SWAP_SEL (3.9) is 1’b1
0 = Selects partner channel SERDES TXBCLK clock
1 = Selects partner channel SERDES RXBCLK clock (Default 1’b1)
See Figure 1-5
ACCESS
RW
RW
RW
RW
48
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