TLK6002 Datasheet, PDF (2/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TLK6002 20-bit parallel interface operates in 1.5V or 1.8V HSTL single-ended format. The 20-bit interface
allows low speed signals on the parallel side and therefore enabling the use of low cost FPGA in the
system design. The parallel interface can be programmed to be in SDR (Single Data Rate) or DDR
(Double Data Rate) modes. The line rate may be set to full (≤6.25Gbps), half (≤3.75Gbps), quarter
(≤1.88Gbps) or eighth (≤0.94Gbps). The line rate can be set using either device inputs or software control
registers.
The TLK6002 performs data conversion parallel-to-serial, serial-to-parallel and clock extraction as a
physical layer interface device. The serial transceiver interface operates at a maximum serial data rate of
6.25 Gbps.
TLK6002 accepts single-ended HSTL signals at its parallel transmit and receive data buses. If the internal
8B/10B coding and decoding are enabled, TDA/B_[19:0] are latched by TXCLK_A/B and sent to the
internal 8b/10b encoder, where the resulting encoded words are serialized and transmitted differentially
using a line clock derived from the SERDES reference clock at the desired line rate. If the internal coding
and decoding are disabled, TDA/B_[19:0] are defined as 20-bits of data being serialized and transmitted
unmodified according to the desired line rate.
The receive direction performs the serial-to-parallel conversion on the input serial data synchronizing the
resulting 20-bit parallel data to the recovered byte clock (RXCLK_A/B). The optionally decoded receive
data is available on the RDA/B_[19:0] output signals.
The serial transmitter and receiver are implemented using differential Current Mode Logic (CML) with
integrated termination resistors.
The TLK6002 provides two local (parallel side) and two remote (serial side) loopback modes for self-test
and system diagnostic purposes.
The TLK6002 has an integrated loss of signal (LOS) detection function, which is asserted in conditions
where the serial input signal does not have sufficient voltage amplitude (≤75 mV_dfpp). Note that the input
signal must be ≥150 mV_dfpp when loss of signal replacement of the receive datapath data is enabled
(register bit 6.6).
2
Introduction
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