TLK6002 Datasheet, PDF (17/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

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2.2 Device Pinout Diagram
Table 2-3. Device Pinout Diagram – (Top View)
TLK6002
SLLSE34 – MAY 2010
1
A DGND
B RDA_17
C RDA_9
D RDA_19
E VDDQA
F RXCLK_A
G DGND
H TDA_19
J TDA_14
K VDDQA
L VREFTA
M RESTA
N VDDQA
P TXCLK_A
R DGND
T
MDC
U DGND
V RESET_N
2
RDA_12
3
VDDQA
VDDQA
RDA_16
RDA_18
RDA_11
DGND
RDA_15
RDA_10
DGND
RDA_14
VDDQA
RDA_13
RDA_4
TDA_17
TDA_15
DGND
TDA_18
DGND
DGND
TDA_8
TDA_12
TDA_5
TDA_10
DGND
TDA_6
TDA_4
VDDQA
TDA_1
REFCLK_B
_SEL
MDIO
RATE_A2
TMS
TRST_N
RATE_A0
PRBSA_PA
SS
4
DGND
DGND
VDDQA
5
REFCLK_0
_N
REFCLK_0
_P
DGND
RDA_7
RDA_6
DGND
RDA_2
RDA_8
RDA_5
VDDQA
RDA_0
RDA_3
VDDQA
RDA_1
DGND
TDA_16
VDDQA
TDA_13
TDA_11
TDA_9
TDA_7
DGND
TDA_2
TDA_3
TDA_0
GPI0
DGND
RATE_A1
DVDD
LOSA
AMUXA
CODEA_EN
AGND
6
DGND
DGND
REFCLK_1
_P
REFCLK_1
_N
VDD_CP1_
PFD1
VDD_PRI_I
N1
VDD_FBIN
VDD_SEC_
IN1
CLK_OUT_
P
DGND
DVDD
VDDQA
DVDD
VDDQA
REFCLK_A
_SEL
PD_TRXA_
N
AVDD
TXAN
7
CGND
VDD_XTAL
LF1B
LF1A
VDD_PLL1
FBINN
FBINP
CGND
CLK_OUT_
N
RESETN
VDDQA
DGND
DGND
DGND
VDDO3
VDDRA
AGND
TXAP
8
XTALP
XTALN
VDD_SREF
CGND
CGND
9
CGND
VDD_PRI_I
N2
VDD_SEC_
IN2
SYNTHREF
CGND
10
PRI_REF2P
PRI_REF2N
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
CGND
Y3N
VDD_Y4
Y3P
VDD_Y3
Y0N
VDD_Y2
RESRA
VDDQA
VPP
DVDD
GPI1
VDDO1
PRTAD3
DGND
DVDD
DGND
VDD33
DGND
DGND
DGND
DGND
DVDD
AGND
DVDD
VDDD
AVDD
AVDD
RXAN
RXAP
AGND
VDDT
AGND
RXBP
11
CGND
VDD_PLL2
VDD_CP2_
PFD2
CGND
CGND
CGND
CGND
Y0P
VDD_Y1
PRTAD1
PRTAD0
DGND
DGND
DGND
AGND
VDDD
AVDD
RXBN
12
CGND
LF2B
LF2A
CGND
VDD_VCO
VDD_RF_P
S
CGND
CGND
VDD_Y0
PRTAD2
VDDQB
DVDD
DGND
DGND
DVDD
VDDRB
TXBP
VDDT
13
RC1
AMUX
CGND
RFOUTN
RFOUTP
VDD18
VDD_DIG_
IO
SCL
PDN
SDO
DVDD
VDDQB
DVDD
VDDQB
VDDO2
AVDD
TXBN
AGND
14
15
RC3
DGND
RC2
CMSEL
RDB_6
VDDQB
CS_N
SDI
RDB_5
RDB_4
VDDQB
RDB_0
RDB_8
RDB_1
DGND
RESRB
RDB_2
VDDQB
DGND
TDB_13
TDB_15
VDDQB
TDB_11
TDB_9
TDB_7
DGND
TDB_1
TDB_2
TDO
AGND
AVDD
AMUXB
TDI
CLK_OUT_
SEL
PD_TRXB_
N
PRTAD4
16
RDB_7
RDB_12
RDB_11
RDB_10
DGND
RDB_15
RDB_3
DGND
TDB_17
TDB_14
TDB_12
TDB_10
TDB_6
VDDQB
PRBS_EN
TCK
RATE_B2
CODEB_EN
17
RDB_13
18
DGND
VDDQB
RDB_16
RDB_17
RDB_9
DGND
RDB_18
RDB_19
VDDQB
RDB_14
VDDQB
RXCLK_B
DGND
TDB_18
TDB_19
TDB_16
TDB_5
DGND
VDDQB
VDDQB
VREFTB
TDB_4
RESTB
DGND
VDDQB
TDB_8
TDB_0
TDB_3
DGND
TESTEN
TXCLK_B
RATE_B1
LOSB
RATE_B0
PRBSB_PA
SS
2.3 CPRI/OBSAI Specific Operation Modes
The TLK6002 contains an internal low-jitter high quality oscillator that is used as a frequency multiplier for
the serdes and other internal circuits of the device. The rate pins (and mdio registers) as well as the
SERDES PLL multiplier are used to program the line rate and the REFCLK frequency for various
applications. See Appendix B for more details on SERDES reference clock, rate, and multiplier selection
(rates beyond the CPRI/OBSAI specific rates).
The TLK6002 is optimized for operation at a serial data rate of 470 Mbit/s through 6.25 Gbit/s. The
external differential reference clock has a large operating frequency range allowing support for many
different applications. The reference clock frequency must be within ±200 PPM of the incoming serial data
rate (±100 PPM of nominal data rate), and have less than 40ps of jitter. Table 2-4 and Table 2-5 show a
summary of frequency ranges used for the CPRI and OBSAI applications. The transmit parallel input clock
must be frequency locked (0 ppm) to the supplied/selected reference clock (REFCLK_0/1_P/N) frequency.
Table 2-4. CPRI Line Rate Selection⁽¹⁾
LINE RATE
(Mbps)
SERDES PLL
MULTIPLIER VALUE
RATE SELECT (PINS OR
REGISTER VALUE)
TXCLK_A/B
(MHz)
REFCLKP/N
(MHz)
6144.00
20/25
Full
307.2
153.60/122.88
4915.20
16/20
Full
245.76
153.60/122.88
3072.00
20/25
Half
153.6
153.60/122.88
2457.60
16/20
Half
122.88
153.60/122.88
1228.80
16/20
Quarter
61.44
153.60/122.88
614.40
16/20
Eighth
30.72
153.60/122.88
(1) In DDR mode TX_CLK frequencies will be half the values in the table above. The table above indicate two possible REFCLK
frequencies, 153.60MHz and 122.88MHz which can be used based on the application preference. The Serdes PLL Multiplier (MPY) has
been given for each REFCLK frequency respectively. Note that Channel A and B are independent, and their application rates and
references clocks are separate.
Copyright © 2010, Texas Instruments Incorporated
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