TLK6002 Datasheet, PDF (90/96 Pages) Texas Instruments – Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver

TLK6002
SLLSE34 – MAY 2010
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8 Appendix D – Device Latency Specification
The following tables show the absolute device latency in each operation mode.
Table 8-1. Device Absolute Transmit Latency – SDR and DDR Modes
SDR TRANSMIT ABSOLUTE LATENCY (Serial Bit Times)
Note: TX FIFO, in register 6.14:12, defaults to Auto Selection Mode. This table contains latencies when the TX FIFO is set in the minimum
latency mode (6.14:12 = 3'b000).
LATENCY COMPONENTS
Item
Minimum Maximum
Description
A
8
12
Sampling edge of TXCLK_* to TX FIFO Input Register
B
10
40
TX FIFO Input Register to TX FIFO Output Register
C
20
20
TX FIFO Output Register to 8b/10b Encoder Register
D
10
10
8b/10b Encoder Register to PMA Retime Register
E
20
20
PMA Retime Register to TX SERDES Input Register
F
16
22
TX SERDES Input Register to Serialized Output Bit
Bit Detail
TX*_[19]
TX*_[10]
TX*_[9]
TX*_[0]
Latency
0
9
10
19
Minimum
84
93
94
103
Maximum
124
133
134
143
Assumption: TX*_[19] is first transmitted bit. TX*_[19:10] is first transmitted
symbol. 8b/10b encoder is enabled. Disabling 8b/10b encoder reduces latency
by 10 bit times.
Latency
Summary
TX*_[19]
TX*_[10]
TX*_[9]
TX*_[0]
Encoder Enabled
Minimum Maximum
84
124
93
133
94
134
103
143
Encoder Disabled
Minimum Maximum
74
114
83
123
84
124
93
133
DDR TRANSMIT ABSOLUTE LATENCY (Serial Bit Times)
DDR Transmit Latency is the same as transmit SDR mode, except that all numbers are 8 to12 bit times larger.
Latency
Summary
Encoder Enabled
Minimum Maximum
Encoder Disabled
Minimum Maximum
TX*_[19]
92
136
82
126
TX*_[10]
101
145
91
135
TX*_[9]
102
146
92
136
TX*_[0]
111
155
101
145
90
Appendix D – Device Latency Specification
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